Intel® Stratix® 10 Device Design Guidelines

ID 683738
Date 8/24/2022
Document Table of Contents

Recommended Timing Optimization and Analysis Assignments

Table 70.  Recommended Timing Optimization and Analysis Assignments Checklist
Number Done? Checklist Item
1   Turn on Optimize multi-corner timing on the Fitter Settings page in the Settings dialog box.
2   Use create_clock and create_generated_clock to specify the frequencies and relationships for all clocks in your design.
3   Use set_input_delay and set_output_delay to specify the external device or board timing parameters.
4   Use derive_clock_uncertainty to automatically apply inter-clock, intra-clock, and I/O interface uncertainties.
5   Use check_timing to generate a report on any problem with the design or applied constraints, including missing constraints.
6   Use set_false_path or set_clock_groups for asynchronous paths.

These assignments and settings are important for large designs such as those in Intel® Stratix® 10 devices.

When you turn on the Optimize multi-corner timing option, the design is optimized to meet its timing requirements at all timing process corners and operating conditions. Therefore, turning on this option helps create a design implementation that is more robust across PVT variations.

In your Timing Analyzer .sdc constraints file, apply the recommended constraints to your design.