Board-Level Simulation and Advanced I/O Timing Analysis
|1||Perform board-level simulation using IBIS models (when available).|
|2||Configure board trace models for Intel® Quartus® Prime advanced I/O timing analysis.|
To ensure that the I/O signaling meets receiver threshold levels on your board setup, perform full board routing simulation with third-party board-level simulation tools using an IBIS model.
When this feature is available in the Intel® Quartus® Prime software, select IBIS under Board-level signal integrity analysis on the Board-Level page in EDA Tool Settings of the Settings dialog box.
When you include an FPGA device with high-speed interfaces in a board design, knowing the signal integrity and board routing propagation delay is vital for proper system operation. You should analyze board level timing as part of the I/O and board planning, especially for high-speed designs.
You can configure board trace models of selected I/O standards and generate “board-aware” signal integrity reports with the Intel® Quartus® Prime software. When Enable Advanced I/O Timing is turned on (Timing Analyzer page in the Settings dialog box), the Timing Analyzer uses simulation results for the I/O buffer, package, and the board trace model to generate more accurate I/O delays and extra reports to give insight into signal behavior at the system level. You can use these advanced timing reports as a guide to make changes to the I/O assignments and board design to improve timing and signal integrity.
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