Intel® Stratix® 10 Device Design Guidelines

ID 683738
Date 8/24/2022
Document Table of Contents

PLL Feature Guidelines

Table 55.  PLL Feature Guidelines Checklist
Number Done? Checklist Item
1   Enable PLL features and check settings in the parameter editor.

Based on your system requirements, define the required clock frequencies for your FPGA design, and the input frequencies available to the FPGA. Use these specifications to determine your PLL scheme. Use the Intel® Quartus® Prime parameter editor to enter your settings in IOPLL Intel® FPGA IP core, and check the results to verify whether particular features and input/output frequencies can be implemented in a particular PLL.

Intel® Stratix® 10 devices contain fractional PLLs in addition to I/O PLLs. You can configure fractional PLLs as integers or as enhanced fractional PLLs.

You can use I/O PLLs and fractional PLLs to reduce the number of oscillators required on the board, as well as to reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source. In addition, you can use fractional PLLs for transmit clocking for transceivers.

Intel® Stratix® 10 device PLLs are feature rich, and support advanced capabilities such as clock feedback modes, switchover, and dynamic phase shifting.