Intel® Stratix® 10 Device Design Guidelines

ID 683738
Date 8/24/2022
Document Table of Contents

Power Pin Connections and Power Supplies

Table 27.  Power Pin Connections and Power Supplies Checklist
Number Done? Checklist Item
1   Connect all power pins correctly as specified in the Intel® Stratix® 10 Device Family Pin Connection Guidelines.
2   Connect VCCIO pins and VREF pins to support each bank I/O standards.
3   Explore unique requirements for FPGA power pins or other power pins on your board, and determine which devices on your board can share a power rail.
4   Follow the suggested power supply sharing and isolation guidance, and the specific guidelines for each pin in the Intel® Stratix® 10 Device Family Pin Connection Guidelines.
5   Refer to AN 692: Power Sequencing Considerations for Intel® Arria® 10 and Intel® Stratix® 10 Devices to understand the power sequencing design requirements.
6   For SmartVID devices (–1V, –2V, and –3V speed grade devices), you must use PMBus-compliant voltage regulator to supply the VCC and VCCP pins. The recommended PMBus-compliant voltage regulator is LTM4677. For more details, refer to the Intel® Stratix® 10 Power Management User Guide.

Intel® Stratix® 10 devices require various voltage supplies depending on your design requirements.

Intel® Stratix® 10 devices support a wide range of industry I/O standards. The device output pins do not meet the I/O standard specifications if the VCCIO level is out of the recommended operating range for the I/O standard.

Voltage reference (VREF) pins serve as voltage references for certain I/O standards. The VREF pin is used mainly for a voltage bias and does not source or sink much current. The voltage can be created with a regulator or a resistor divider network.

VREFP_ADC and VREFN_ADC pins are dedicated precision analog voltage reference pins. Both the VREFP_ADC and VREFN_ADC pins need to be grounded to enable the internal ADC reference.