Intel® Stratix® 10 Device Design Guidelines

ID 683738
Date 8/24/2022
Document Table of Contents

I/O Simultaneous Switching Noise

Table 59.  I/O Simultaneous Switching Noise Checklist
Number Done? Checklist Item
1   Reduce the number of pins that switch the voltage level at exactly the same time whenever possible.
2   Use differential I/O standards and lower-voltage standards for high-switching I/Os.
3   Use lower drive strengths for high-switching I/Os. The default drive strength setting might be higher than your design requires.
4   Reduce the number of simultaneously switching output pins within each bank. Spread output pins across multiple banks if possible.
5   Spread switching I/Os evenly throughout the bank to reduce the number of aggressors in a given area to reduce SSN (when bank usage is substantially below 100%).
6   Separate simultaneously switching pins from input pins that are susceptible to SSN.
7   Place important clock and asynchronous control signals near ground signals and away from large switching buses.
8   Avoid using I/O pins one or two pins away from PLL power supply pins for high-switching or high-drive strength pins.
9   Use staggered output delays to shift the output signals through time, or use adjustable slew rate settings.
10   Limit the number of unterminated SSO pins within the I/O bank where the PLL output clock resides to achieve the Intel® Stratix® 10 I/O PLL clock output jitter performance specification.

SSN is a concern when too many I/Os (in close proximity) change voltage levels at the same time. Plan the I/O and clock connections according to the recommendations.

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