Intel® Stratix® 10 Device Design Guidelines

Download PDF
ID 683738
Date 8/24/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Design Guidelines
Intel® Stratix® 10 Device Design Guidelines x
Design Flow System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Security Considerations Design Entry Design Implementation, Analysis, Optimization, and Verification Document Revision History for Intel® Stratix® 10 Device Design Guidelines
System Specification x
Design Specifications IP Selection Platform Designer
Device Selection x
Device Variant PLLs and Clock Routing Logic, Memory, and Multiplier Density I/O Pin Count, LVDS Channels, and Package Offering Speed Grade Vertical Device Migration
Early System and Board Planning x
Power and Thermal Estimation Thermal Management and Design Temperature Sensing for Thermal Management Voltage Sensor Planning for Device Configuration Planning for On-Chip Debugging
Planning for Device Configuration x
Device Power Cycling and Reconfiguration Configuration Scheme Selection Configuration Features Intel® Quartus® Prime Configuration Settings
Configuration Scheme Selection x
Serial Configuration Devices Download Cables
Intel® Quartus® Prime Configuration Settings x
Optional Configuration Pins Dual Purpose Configuration Pins
Planning for On-Chip Debugging x
On-Chip Debugging Tools Planning Guidelines for Debugging Tools
Pin Connection Considerations for Board Design x
Device Power-Up Power Pin Connections and Power Supplies Configuration Pin Connections Board-Related Intel® Quartus® Prime Settings Signal Integrity Considerations Board-Level Simulation and Advanced I/O Timing Analysis
Power Pin Connections and Power Supplies x
Decoupling Capacitors PLL Board Design Guidelines Transceiver Board Design Guidelines
Configuration Pin Connections x
Configuration Pin Voltage Level Clock Trace Signal Integrity JTAG Pins MSEL Configuration Mode Pins Other Configuration Pins
JTAG Pins x
JTAG Pin Connections Download Cable Operating Voltage JTAG Signal Buffering
Board-Related Intel® Quartus® Prime Settings x
Unused Pins
Signal Integrity Considerations x
High-Speed Board Design Voltage Reference Pins Simultaneous Switching Noise I/O Termination
I/O and Clock Planning x
Making FPGA Pin Assignments Early Pin Planning and I/O Assignment Analysis I/O Features and Pin Connections Clock and PLL Selection PLL Feature Guidelines Clock Control Features I/O Simultaneous Switching Noise
I/O Features and Pin Connections x
I/O Signaling Type Selectable Standards and Flexible I/O Banks Memory Interfaces Dual-Purpose and Special Pin Connections Intel® Stratix® 10 I/O Features
PLL Feature Guidelines x
Clock Feedback Mode Clock Outputs
Design Entry x
Design Recommendations Using IP Cores Reconfiguration Recommended HDL Coding Styles
Design Implementation, Analysis, Optimization, and Verification x
Selecting a Synthesis Tool Device Resource Utilization Reports Intel® Quartus® Prime Messages Timing Constraints and Analysis Area and Timing Optimization Preserving Performance and Reducing Compilation Time Designing with Intel® Hyperflex™ Simulation Power Analysis Power Optimization
Timing Constraints and Analysis x
Recommended Timing Optimization and Analysis Assignments
Power Optimization x
Device and Design Power Optimization Techniques Intel® Quartus® Prime Power Optimization Techniques
Device and Design Power Optimization Techniques x
Device Speed Grade Clock Power Management Memory Power Reduction I/O Power Guidelines
Intel® Quartus® Prime Power Optimization Techniques x
Power Optimization Advisor
Intel® Stratix® 10 Device Design Guidelines

Document Revision History for Intel® Stratix® 10 Device Design Guidelines

Document Version Changes
2022.08.24
  • Updated Design Specification section.
  • Updated Power Pin Connections and Power Supplies section.
2021.04.22
  • Added information about Intel® Stratix® 10 devices with -BK suffix that support black key provisioning in the Security Considerations section.
  • Updated the Authentication and Advanced Security Features Support for Intel® Stratix® 10 Devices table.
    • Added description about security features in Intel® Stratix® 10 devices that support advanced security.
    • Added Intel® Stratix® 10 GX 10M device.
2020.12.14 Added checklist item on Quad SPI flash operations in the Planning for Device Configuration Checklist table.
2020.06.30
  • Updated the Planning for Device Configuration Checklist table.
    • Added checklist item on Intel® Stratix® 10 GX 10M devices configuration.
    • Added checklist items on nCONFIG operation.
  • Added Device Power Cycling and Reconfiguration section.
  • Updated checklist item to add guidelines on VCCIO when using the Avalon® -ST ×32 or ×16 configuration scheme in the Configuration Pin Voltage Level Checklist table.
  • Removed all instances of EPCQ-L. This flash device is obsolete. Updated the serial flash information in the following sections:
    • Serial Configuration Devices
    • Configuration Pin Voltage Level
  • Removed guidelines related to SD/MMC device configuration in the following sections:
    • Removed SD/MMC flash memories support in the Configuration Pin Voltage Level section.
    • Removed SDMMC_CFG_CCLK pin in the Clock Trace Signal Integrity section.
  • Changed Early Power Estimator (EPE) to Intel FPGA Power and Thermal Calculator (PTC).
2019.12.16
  • Added checklist items on I/O pins support limitation for banks 3A, 3C, and 3D in the Selectable Standards and Flexible I/O Banks Checklist table.
  • Added Security Considerations section.
2019.10.10
  • Updated checklist item on configuration guidelines and additional clock requirements in the Planning for Device Configuration Checklist table.
  • Added checklist items on I/O pins support limitation for LVDS SERDES in the Selectable Standards and Flexible I/O Banks Checklist table.
  • Updated checklist item on DQS and DQ pins and added checklist item on I/O pins support limitations for EMIF in the Memory Interfaces Checklist table. Updated the description on DQS and DQ pins for EMIF supported banks.
2019.06.24
  • Added a checklist item on PMBus-compliant voltage regulator for SmartVID devices in the Power Pin Connections and Power Supplies Checklist table.
  • Added a link to the PDN website in the Decoupling Capacitors section.
  • Added a checklist item on unterminated SSO pins in the I/O Simultaneous Switching Noise Checklist table.
2019.04.02
  • Added a checklist item on Intel® Stratix® 10 Reset Release IP in the Planning for Device Configuration Checklist table.
  • Updated the guidelines on physical synthesis optimizations in the Area and Timing Optimization section.
2018.09.24
  • Added a checklist item on configuration guidelines and additional clock requirements for designs using PCIe, transceiver channels, HPS, High Bandwidth Memory (HBM2) IP core, or SmartVID in the Planning for Device Configuration Checklist table.
  • Added a checklist item on SmartVID connection and the VCC voltage regulator in the Other Configuration Pins Checklist table.
2018.05.07
  • Updated checklist item in the Device Variant Checklist table.
  • Added links to transceiver documents in the following sections:
    • Speed Grade
    • Vertical Device Migration
    • Transceiver Board Design Guidelines
  • Removed NAND configuration scheme.
  • Renamed the following IP cores as per Intel rebranding:
    • Renamed Intel FPGA S10 Temperature Sensor IP core to Temperature Sensor Intel Stratix 10 FPGA IP core.
    • Renamed Virtual JTAG IP core to Virtual JTAG Intel FPGA IP core.
    • Renamed SLD_VIRTUAL_JTAG IP core to SLD_VIRTUAL_JTAG Intel FPGA IP core.
    • Renamed Stratix 10 External Memory Interfaces IP core to External Memory Interfaces Intel Stratix 10 FPGA IP core.
    • Renamed Stratix 10 Intel FPGA PHYLite for Parallel Interfaces IP core to PHYLite for Parallel Interfaces Intel Stratix 10 FPGA IP core.
    • Renamed Intel FPGA IOPLL IP core to IOPLL Intel FPGA IP core.
    • Renamed Stratix 10 Clock Control IP core to Clock Control Intel Stratix 10 FPGA IP core.
  • Removed the LPM_CONSTANT IP core. Not supported in the Intel® Stratix® 10 devices.
Date Version Changes
December 2017 2017.12.12
  • Updated checklist item in the Design Specifications Checklist table.
  • Updated checklist item in the IP Selection Checklist table.
  • Updated checklist item in the PLLs and Clock Routing Checklist table.
  • Updated the Logic, Memory, and Multiplier Density section.
  • Added checklist item in the Vertical Device Migration Checklist table.
  • Added external TSD information in the Temperature Sensing for Thermal Management section.
  • Added thermal information in the following sections:
    • Early Power Estimation
    • Thermal Management and Design
    • Temperature Sensing for Thermal Management
  • Changed the section title from Data Compression to Configuration Bitstream Compression.
  • Updated the Optional Configuration Pins section.
  • Added description for the Signal Tap Embedded Logic Analyzer in the On-Chip Debugging Tools section.
  • Added checklist item to the Power Pin Connections and Power Supplies Checklist table.
  • Updated checklist item in the Board-Related Intel® Quartus® Prime Settings Checklist table.
  • Updated the links in the Memory Interfaces section.
  • Updated the Dual-Purpose and Special Pin Connections section.
  • Updated the Design Entry section.
  • Removed information on Design Assistant in the Design Recommendations section.
  • Updated the Reconfiguration section.
  • Removed information on formal verification in the Design Implementation, Analysis, Optimization, and Verification section.
  • Updated report locations in the Device Resource Utilization Reports section.
  • Updated the Timing Constraints and Analysis section.
  • Updated the Recommended Timing Optimization and Analysis Assignments Checklist table.
    • Removed checklist item on derive_pll_clocks.
    • Added checklist item on set_false_path and set_clock_groups.
  • Updated the Area and Timing Optimization section.
  • Updated description on Hyper-Registers in the Designing with Intel® Hyperflex™ section.
  • Removed information on NativeLink in the Simulation section.
  • Removed information on programmable power tiles in the following section:
    • Power Optimization
    • Device Speed Grade
    • Intel® Quartus® Prime Power Optimization Techniques
  • Removed the following sections:
    • Device-Wide Output Enable Pin
    • Register Power-Up Levels and Control Signals
    • Formal Verification
  • Updated the following terms:
    • Changed Qsys to Platform Designer
    • Changed OpenCore Plus to Intel® FPGA IP Evaluation Mode
    • Changed TimeQuest Timing Analyzer to Timing Analyzer
    • Changed BluePrint Platform Designer to Interface Planner
  • Updated IP name from Altera PHYLite for Parallel Interfaces to PHY Lite for Parallel Interfaces.
  • Rebranded as Intel® .
February 2017 2017.02.13
  • Removed Start I/O Assignment Analysis command in Early Pin Planning and I/O Assignment Analysis section.
  • Removed incremental compilation feature. Removed the following topics:
    • Planning for Hierarchical and Team-Based Design
    • Planning Design Partitions
    • Planning in Bottom-Up and Team-Based Flows
    • Creating a Design Floorplan
  • Updated feature names.
    • Changed SignalProbe to Signal Probe
    • Removed PowerPlay text from tool name
October 2016 2016.10.31 Initial release.
Level Two Title