Design Flow System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Security Considerations Design Entry Design Implementation, Analysis, Optimization, and Verification Document Revision History for Intel® Stratix® 10 Device Design Guidelines
Other Configuration Pins
|1||Use the SDM pins which have multiple configuration functions if power management function is required.|
|2||When a –V device is used, you must enable the SmartVID connection between the device and the VCC voltage regulator to allow the FPGA to directly control its core voltage requirements. Refer to the Intel® Stratix® 10 Device Family Pin Connection Guidelines and Intel® Stratix® 10 Power Management User Guide for the pin connections and implementation.|
Most of the SDM pins have multiple configuration functions, depending on the configuration schemes used. Some SDM pins also have power management functions. If power management function is required, choose the SDM pins which do not need to be used for configuration to implement the power management function.
Connect the SDM pins on your board to the external configuration host or configuration device based on the configuration scheme to be used. If more than one configuration scheme are used, ensure there is no contention between configuration host or configuration devices connected to the SDM pins.
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