Planning for Device Configuration
|1||Consider whether you require multiple configuration schemes.|
|2||To avoid configuration failure, follow the configuration guidelines and additional clock requirements if your design is using PCIe, transceiver channels, HPS EMIF, High Bandwidth Memory (HBM2) IP core, or SmartVID. Refer to the Intel® Stratix® 10 Configuration User Guide and Intel® Stratix® 10 Power Management User Guide for the guidelines.|
|3||Intel strongly recommends using the Intel® Stratix® 10 Reset Release IP in your design to provide a known initialized state for your logic to begin operation. The Reset Release IP is available in the Intel® Quartus® Prime software version 19.1 and later. Refer to the Intel® Stratix® 10 Configuration User Guide for the guidelines.|
|4||Each die in the Intel® Stratix® 10 GX 10M devices has its own configuration pins. Configure each die separately by using the dedicated configuration bit stream or .sof file. The device cannot be configured using a single .sof file because each die has a unique JTAG ID.|
|5||Ensure nCONFIG is connected in following manner:
|6||Ensure that nCONFIG is not directly driven by FPGA, HPS I/Os, or any component that has dependency on FPGA or HPS I/Os.|
|7||For Intel® Stratix® 10 devices, do not reset the Quad SPI flash when used as the configuration device and data storage device with FPGA. Resetting the Quad SPI flash during the FPGA configuration and reconfiguration, or during the READ/WRITE/ERASE operations of the Quad SPI, causes undefined behavior for Quad SPI flash and the FPGA. To recover from the unresponsive behavior, you must power cycle your device. To reset the Quad SPI flash via the external host, you must first complete the FPGA configuration and reconfiguration, or a Quad SPI operation, and only then toggle the reset. The Quad SPI operation is complete when the exclusive access to the Quad SPI flash is closed by issuing the QSPI_CLOSE command via the Mailbox Client Intel® FPGA IP or CLOSE command via the Serial Flash Mailbox Client Intel® FPGA IP.|
Intel® Stratix® 10 devices are based on SRAM cells. You must download configuration data to the Intel® Stratix® 10 device each time the device powers up, because SRAM is volatile. Consider whether you require multiple configuration schemes, such as one for debugging or testing and another for the production environment.
Choosing the device configuration method early allows system and board designers to determine what companion devices, if any, are required for the system. Your board layout also depends on the configuration method you plan to use for the programmable device, because different schemes require different connections.
In addition, Intel® Stratix® 10 devices offer advanced configuration features, depending on your configuration scheme. Intel® Stratix® 10 devices also include optional configuration pins and a reconfiguration option that you should choose early in the design process (and set up in the Intel® Quartus® Prime software), so you have all the information required for your board and system design.
Device Power Cycling and Reconfiguration
Configuration Scheme Selection
Intel Quartus Prime Configuration Settings
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