Intel® Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 12/29/2023
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Document Table of Contents x
Intel® Stratix® 10 Device Family Pin Connection Guidelines
Intel® Stratix® 10 Device Family Pin Connection Guidelines x
Intel® Stratix® 10 Core Pins Intel® Stratix® 10 High Bandwidth Memory (HBM) Pins H-Tile and L-Tile Pins Intel® Stratix® 10 E-Tile Pins Intel® Stratix® 10 P-Tile Pins Intel® Stratix® 10 Hard Processor System (HPS) Pins Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices Document Revision History for the Intel® Stratix® 10 Device Family Pin Connection Guidelines
Intel® Stratix® 10 Core Pins x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins 3V Compatible I/O Pins 3.3V I/O Pins Differential I/O Pins External Memory Interface Pins Voltage Sensor Pins Temperature Sensor Pins Reference Pins No Connect and DNU Pins Power Supply Pins Secure Device Manager (SDM) Pins Secure Device Manager (SDM) Optional Signal Pins Notes to Intel® Stratix® 10 Core Pins
Intel® Stratix® 10 High Bandwidth Memory (HBM) Pins x
UIB and eSRAM Pins Intel® Stratix® 10 HBM Power Supply Pins Notes to Intel® Stratix® 10 HBM Pins
H-Tile and L-Tile Pins x
H-Tile and L-Tile Pins
Intel® Stratix® 10 E-Tile Pins x
Intel® Stratix® 10 E-Tile Pins Notes to Intel® Stratix® 10 E-Tile Pins
Intel® Stratix® 10 P-Tile Pins x
Intel® Stratix® 10 P-Tile Power Supply Pins Intel® Stratix® 10 P-Tile Transceiver Pins
Intel® Stratix® 10 Hard Processor System (HPS) Pins x
HPS Supply Pins HPS Oscillator Clock Input Pin HPS JTAG Pins HPS GPIO Pins HPS SDMMC Pins HPS NAND Pins HPS USB Pins HPS EMAC Pins HPS I2C_EMAC and MDIO Pins HPS I2C Pins HPS SPI Pins HPS UART Pins HPS Trace Pins Notes to Intel® Stratix® 10 HPS Pins
Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices x
Example 1— Intel® Stratix® 10 GX Example 2— Intel® Stratix® 10 GX Example 3— Intel® Stratix® 10 GX (only for the HF35 Package) Example 4— Intel® Stratix® 10 GX (only for the HF35 Package) Example 5— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) Example 6— Intel® Stratix® 10 SX (–2L and –3X parts) Example 7— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) Example 8— Intel® Stratix® 10 SX (–2L and –3X parts) Example 9— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 10— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 11— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 12— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 13— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) Example 14— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) Example 15— Intel® Stratix® 10 MX (E-Tile) Example 16— Intel® Stratix® 10 TX (–1V, –2V, and –3V parts) Example 17— Intel® Stratix® 10 TX (–2L and –3X parts) Example 18— Intel® Stratix® 10 DX (–1V, –2V, and –3V parts) Example 19— Intel® Stratix® 10 GX 10M Example 20— Intel® Stratix® 10 GX 10M
Intel® Stratix® 10 Device Family Pin Connection Guidelines

Dedicated Configuration/JTAG Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 2.  Dedicated Configuration/JTAG Pins
Pin Name ( Intel® Stratix® 10 Devices) Pin Name ( Intel® Stratix® 10 GX 10M Device) Pin Functions Pin Description Connection Guidelines
TCK F[1,2]_TCK Input

Dedicated JTAG test clock input pin. This pin can also be used to access the SDM and HPS JTAG chains. For more information, refer to the HPS JTAG Pins.

Connect this pin through a 1-kΩ pull-down resistor to GND.

This pin has an internal 25-kΩ pull-down.

Do not drive voltage higher than the VCCIO_SDM supply for the TCK pin. The TCK input pin is powered by the VCCIO_SDM supply.

TMS F[1,2]_TMS Input

Dedicated JTAG test mode select input pin. This pin can also be used to access the SDM and HPS JTAG chains. For more information, refer to the HPS JTAG Pins.

Connect this pin to a 1-kΩ - 10-kΩ pull-up resistor to the VCCIO_SDM supply. If the JTAG interface is not used, connect the TMS pin to the VCCIO_SDM supply using a 1-kΩ resistor.

This pin has an internal 25-kΩ pull-up.

Do not drive voltage higher than the VCCIO_SDM supply for the TMS pin. The TMS input pin is powered by the VCCIO_SDM supply.

TDO F[1,2]_TDO Output

Dedicated JTAG test data output pin. This pin can also be used to access the SDM and HPS JTAG chains. For more information, refer to the HPS JTAG Pins.

If the JTAG interface is not used, leave the TDO pin unconnected.
TDI F[1,2]_TDI Input

Dedicated JTAG test data input pin. This pin can also be used to access the SDM and HPS JTAG chains. For more information, refer to the HPS JTAG Pins.

Connect this pin to a 1-kΩ - 10-kΩ pull-up resistor to the VCCIO_SDM supply. If the JTAG interface is not used, connect the TDI pin to the VCCIO_SDM supply using a 1-kΩ resistor.

This pin has an internal 25-kΩ pull-up.

Do not drive voltage higher than the VCCIO_SDM supply for the TDI pin. The TDI input pin is powered by the VCCIO_SDM supply.

nSTATUS F[1,2]_nSTATUS Output This pin is used for synchronization with the configuration host driving nCONFIG and to report errors.
Attention: Ensure that during power up, no external component drives the nSTATUS signal low.

When you are using the Avalon-ST configuration scheme, connect this pin to the configuration host.

For other configuration schemes, you can use this pin to monitor the configuration status.

This pin must be pulled up through a 10-kΩ resistor to VCCIO_SDM for all configuration schemes. This pin has an internal 25-kΩ pull-up.

nCONFIG F[1,2]_nCONFIG Input The nCONFIG pin is used to clear the device and prepare for reconfiguration.

When you use the Avalon-ST configuration scheme, connect this pin to the configuration host.

When you use other configuration schemes, pull this pin to VCCIO_SDM through an external 10-KΩ pull-up resistor. This pin can be used to restart configuration by driving it low and then high again. Ensure that you follow all the requirements for the nCONFIG operation as specified in the Intel® Stratix® 10 Configuration User Guide and Intel® Stratix® 10 Device Design Guidelines.

OSC_CLK_1 F[1,2]_OSC_CLK_1 Input This pin is used as the clock for device configuration and transceiver calibration.

You must provide an external clock source to this pin if you are using transceivers.

If you choose to use the external clock source for configuration and/or instantiate any transceivers in your design, you must provide a 25-MHz, 100-MHz, or 125-MHz free-running clock source to this pin and enable it in the Intel® Quartus® Prime software when you compile your design. If you are using the internal oscillator for configuration and do not instantiate any transceivers in your design, leave this pin unconnected.

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