Intel® Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 6/25/2022
Public
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Secure Device Manager (SDM) Optional Signal Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Note: In the SDM Optional Signal Pins table, the Intel® Stratix® 10 GX 10M device only supports the AVSTx8 configuration scheme.
Table 14.  SDM Optional Signal Pins
Signal Name ( Intel® Stratix® 10 Devices) Signal Name ( Intel® Stratix® 10 GX 10M Device) Signal Description Connection Guidelines Configuration Schemes
ASx4 AVSTx8 AVSTx16 AVSTx32
PWRMGT_SCL F[1,2]_PWRMGT_SCL

PMBus Power Management Clock.

This pin is used as the clock pin for the PMBus interface.

This pin requires a pull-up resistor to the 1.8V VCCIO_SDM supply. Intel® recommends a pull-up value of 5.1-kΩ to 10-kΩ depending on the loading of this pin. Use the voltage level translators when interfacing to the PMBus interfaces requiring voltages other than 1.8V.

Connect this pin to the PMBus clock pin of your regulator.

When a –V device is used, you must enable the SmartVID connection between the device and the VCC voltage regulator to allow the FPGA to directly control its core voltage requirements. You can do this by connecting the PWRMGT_SCL and PWRMGT_SDA signals to the VCC voltage regulator for the PMBus master mode and the PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT signals to the external master controller for the PMBus slave mode.

When the PWRMGT_SCL pin function of the SDM_IO pin is set to the PMBus, it is set to open-drain.

SDM_IO0

SDM_IO14

SDM_IO0

SDM_IO0

SDM_IO14

SDM_IO0

SDM_IO14

PWRMGT_SDA F[1,2]_PWRMGT_SDA

PMBus Power Management Serial Data.

This pin is used as the data pin for the PMBus interface.

This pin requires a pull-up resistor to the 1.8V VCCIO_SDM supply. Intel® recommends a pull-up value of 5.1-kΩ to 10-kΩ depending on the loading of this pin. Use the voltage level translators when interfacing to the PMBus interfaces requiring voltages other than 1.8V.

Connect this pin to the PMBus data pin of your regulator.

When a –V device is used, you must enable the SmartVID connection between the device and the VCC voltage regulator to allow the FPGA to directly control its core voltage requirements. You can do this by connecting the PWRMGT_SCL and PWRMGT_SDA signals to the VCC voltage regulator for the PMBus master mode and the PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT signals to the external master controller for the PMBus slave mode.

When the PWRMGT_SDA pin function of the SDM_IO pin is set to the PMBus, it is set to open-drain.

SDM_IO11

SDM_IO12

SDM_IO16

SDM_IO12

SDM_IO16

SDM_IO11

SDM_IO12

SDM_IO16

SDM_IO11

SDM_IO12

SDM_IO16

PWRMGT_ALERT

PMBus Power Management Alert.

This pin is used as the ALERT function for the PMBus interface when the Intel® Stratix® 10 –V is the PMBus slave.

This pin requires a pull-up resistor to the 1.8V VCCIO_SDM supply. Intel® recommends a pull-up value of 5.1-kΩ to 10-kΩ depending on the loading of this pin. Use the voltage level translators when interfacing to the PMBus interfaces requiring voltages other than 1.8V.

Connect this pin to the PMBus ALERT pin of the external master controller.

When using the SmartVID feature with the Intel® Stratix® 10 –V device as a PMBus slave, you must connect the PWRMGT_ALERT signal along with the PWRMGT_SCL and PWRMGT_SDA signals to the PMBus master device to complete the SmartVID power management interface. The PMBus master device reads the VID codes from the Intel® Stratix® 10 slave and programs the voltage regulator to output the correct VID voltage.

When the PWRMGT_ALERT pin function of the SDM_IO pin is set to the PMBus, it is set to open-drain.

SDM_IO0

SDM_IO12

SDM_IO0

SDM_IO9

SDM_IO12

SDM_IO0

SDM_IO9

SDM_IO12

SDM_IO0

SDM_IO12

CONF_DONE F[1,2]_CONF_DONE

The CONF_DONE pin indicates all configuration data has been received.

For the Intel® Stratix® 10 GX 10M device, both F1_CONF_DONE and F2_CONF_DONE pins must be active before use mode can be initiated.

By default, Intel® recommends using the SDM_IO16 pin to implement the CONF_DONE function.

If SDM_IO16 is unavailable, the CONF_DONE function can also be implemented using any unused SDM_IO pins.

Except for SDM_IO0 and SDM_IO16, other SDM_IO pins are required to connect to an external 4.7-kΩ pull-down resistor for the CONF_DONE signal.

Connect the CONF_DONE pin to the external configuration controller when configuring using the Avalon® -ST (AVST) interface.

You have an option to monitor this signal with an external component if you are using the active serial (AS) x4 configuration scheme.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO5

SDM_IO12

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO6

SDM_IO7

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

INIT_DONE F[1,2]_INIT_DONE

The INIT_DONE pin indicates the device has enter user mode upon completion of configuration. When used for this purpose, this pin must be enabled by the Intel® Quartus® Prime software.

When the INIT_DONE function is enabled, this pin will drive high when configuration is completed and the device goes into user mode.

Intel® recommends you to use SDM_IO0 or SDM_IO16 to implement the INIT_DONE function when available as it has an internal weak pull-down for the correct function of INIT_DONE during power up.

If SDM_IO0 and SDM_IO16 are unavailable, SDM_IO5 can also be used for the INIT_DONE function when the configuration mode is set to Avalon® –ST x8 or Avalon® –ST x32 (AVST x8 or AVST x32) as these modes require an external 4.7–kΩ pull-down resistor.

If SDM_IO0, SDM_IO5, and SDM_IO16 are unavailable, the INIT_DONE function can also be implemented using any unused SDM_IO pins provided that an external 4.7–kΩ pull-down resistor is provided for the INIT_DONE signal.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO5

SDM_IO12

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO6

SDM_IO7

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

CvP_CONFDONE

The CvP_CONFDONE pin indicates the device has received the complete bitstream during configuration via protocol (CvP) core image configuration.

When used for this purpose, enable this pin using the Intel® Quartus® Prime software.

Connect this output pin to an external logic that monitors the CvP operation. The VCCIO_SDM power supply must meet the input voltage specification of the receiving side.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO5

SDM_IO7

SDM_IO9

SDM_IO12

SDM_IO16

SEU_ERROR

The SEU_ERROR pin drives high to indicate there is an SEU error message inside the SEU error queue. This pin stays high whenever the error message queue contains one or more error messages.

The SEU_ERROR signal goes low only when the SEU error message queue is empty. When used for this purpose, enable this pin using the Intel® Quartus® Prime software.

Connect this output pin to an external logic that monitors the SEU event.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO5

SDM_IO7

SDM_IO9

SDM_IO12

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

HPS_COLD_nRESET

This is an active low, bidirectional pin. By default, this pin acts as an input pin to the SDM. When asserted externally for at least 5ms, this pin will generate interrupt to the SDM. The SDM will then initiate a cold reset procedure to the HPS and its peripherals. If the cold reset is generated from internal sources (for example, the HPS EL3 software), the SDM will switch this pin to output and drive a pulse to indicate reset. Once the cold reset procedure is complete, this pin will be switched back to input.

Connect this pin through a 1–10-kΩ pull up to the VCCIO_SDM supply. Do not connect this pin to the reset input of any connected quad serial peripheral interface (quad SPI) devices.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO5

SDM_IO7

SDM_IO9

SDM_IO12

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

Direct to Factory Image

Direct to factory input pin.

When using the remote system upgrade feature, this optional pin allows you to choose between factory or application image. Driving logic high into this pin will instruct the device to load factory image, while driving logic low into this pin will instruct the device to load the application image.

Connect this input pin to an external logic that manages the remote system upgrade of the device. By default, the external logic should provide logic low to this pin so that the application image will be the default image of the device, and only switch to factory image if required.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

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