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Intel® Stratix® 10 Core Pins
Intel® Stratix® 10 High Bandwidth Memory (HBM) Pins
H-Tile and L-Tile Pins
Intel® Stratix® 10 E-Tile Pins
Intel® Stratix® 10 P-Tile Pins
Intel® Stratix® 10 Hard Processor System (HPS) Pins
Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices
Document Revision History for the Intel® Stratix® 10 Device Family Pin Connection Guidelines
Clock and PLL Pins
Dedicated Configuration/JTAG Pins
Optional/Dual-Purpose Configuration Pins
3V Compatible I/O Pins
3.3V I/O Pins
Differential I/O Pins
External Memory Interface Pins
Voltage Sensor Pins
Temperature Sensor Pins
Reference Pins
No Connect and DNU Pins
Power Supply Pins
Secure Device Manager (SDM) Pins
Secure Device Manager (SDM) Optional Signal Pins
Notes to Intel® Stratix® 10 Core Pins
Example 1— Intel® Stratix® 10 GX
Example 2— Intel® Stratix® 10 GX
Example 3— Intel® Stratix® 10 GX (only for the HF35 Package)
Example 4— Intel® Stratix® 10 GX (only for the HF35 Package)
Example 5— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts)
Example 6— Intel® Stratix® 10 SX (–2L and –3X parts)
Example 7— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts)
Example 8— Intel® Stratix® 10 SX (–2L and –3X parts)
Example 9— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package)
Example 10— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package)
Example 11— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package)
Example 12— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package)
Example 13— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts)
Example 14— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts)
Example 15— Intel® Stratix® 10 MX (E-Tile)
Example 16— Intel® Stratix® 10 TX (–1V, –2V, and –3V parts)
Example 17— Intel® Stratix® 10 TX (–2L and –3X parts)
Example 18— Intel® Stratix® 10 DX (–1V, –2V, and –3V parts)
Example 19— Intel® Stratix® 10 GX 10M
Example 20— Intel® Stratix® 10 GX 10M
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HPS I2C Pins
Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
In addition to the three I2C_EMAC controllers, there are two additional I2C controllers (I2C0 and I2C1) for dedicated I2C usage in the Intel® Stratix® 10 HPS.
The I2C protocol requires pull-up resistors to VCCIO_HPS on both the serial data and serial clock signals for them to function correctly. The value of the pull-up resistor varies depending on your board loading, but it is typically 4.7-kΩ or lower.
| HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments (select from one of the groups) | |||
|---|---|---|---|---|---|---|
| Group 1 | Group 2 | Group 3 | Group 4 | |||
| I2C0 _SDA | I2C0 Serial Data | I/O | HPS_IOA_5 | HPS_IOA_23 | HPS_IOB_3 | — |
| I2C0 _SCL | I2C0 Serial Clock | I/O | HPS_IOA_6 | HPS_IOA_24 | HPS_IOB_4 | — |
| I2C1 _SDA | I2C1 Serial Data | I/O | HPS_IOA_3 | HPS_IOA_21 | HPS_IOB_7 | HPS_IOB_13 |
| I2C1 _SCL | I2C1 Serial Clock | I/O | HPS_IOA_4 | HPS_IOA_22 | HPS_IOB_8 | HPS_IOB_14 |
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