Intel® Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 6/25/2022
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Reference Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 10.  Reference Pins
Pin Name ( Intel® Stratix® 10 Devices) Pin Name ( Intel® Stratix® 10 GX 10M Device) Pin Functions Pin Description Connection Guidelines

RZQ_[2][A,B,C,F,G,H,I,J,K,L,M,N]

RZQ_[3][A,B,C,D,E,F,G,H,I,J,K,L]

RZQ_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]

RZQ_[3] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]

I/O, bi-directional

Reference pins for I/O banks. The RZQ pins share the same VCCIO with the I/O bank where they are located.

Connect the external precision resistor to the designated pin within the bank. If not required, this pin is a regular I/O pin.

When using OCT, tie these pins to GND through either a 240-Ω or 100-Ω resistor, depending on the desired OCT impedance. For more information about the OCT schemes, refer to the Intel® Stratix® 10 General Purpose I/O User Guide.

When you do not use these pins as dedicated input for the external precision resistor or as I/O pins, leave these pins unconnected.

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