Intel® Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 6/25/2022
Public
Document Table of Contents

HPS UART Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 33.  HPS UART PinsThere are two UART (UART0 and UART1) controllers for the Intel® Stratix® 10 HPS.
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments (select from one of the groups)
Group 1 Group 2 Group 3
UART0_CTS_N

UART0 Clear to Send

See Note 11 in Notes to Intel® Stratix® 10 HPS Pins.

Input HPS_IOA_1 HPS_IOA_21 HPS_IOB_1
UART0_RTS_N

UART0 Request to Send

See Note 11 in Notes to Intel® Stratix® 10 HPS Pins.

Output HPS_IOA_2 HPS_IOA_22 HPS_IOB_2
UART0_TX UART0 Transmit Output HPS_IOA_3 HPS_IOA_23 HPS_IOB_3
UART0_RX UART0 Receive Input HPS_IOA_4 HPS_IOA_24 HPS_IOB_4
UART1_CTS_N

UART1 Clear to Send

See Note 11 in Notes to Intel® Stratix® 10 HPS Pins.

Input HPS_IOA_5 HPS_IOB_5 HPS_IOB_17
UART1_RTS_N

UART1 Request to Send

See Note 11 in Notes to Intel® Stratix® 10 HPS Pins.

Output HPS_IOA_6 HPS_IOB_6 HPS_IOB_18
UART1_TX UART1 Transmit Output HPS_IOA_7 HPS_IOB_7 HPS_IOB_15
UART1_RX UART1 Receive Input HPS_IOA_8 HPS_IOB_8 HPS_IOB_16

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