Intel® Stratix® 10 Device Family Pin Connection Guidelines

ID 683028
Date 12/29/2023
Document Table of Contents

Differential I/O Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 6.  Differential I/O Pins
Note: The I/O pins are tri-stated with a weak pull-up during power up.
Pin Name ( Intel® Stratix® 10 Devices) Pin Name ( Intel® Stratix® 10 GX 10M Device) Pin Functions Pin Description Connection Guidelines

LVDS[2][A,B,C,D,E, F,G,H,I,J,K,L,M,N]_[1:24][p,n]


LVDS[2][A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_[1:24][p,n] LVDS[3][A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_[1:24][p,n] I/O, RX/TX channel These are true LVDS receiver and transmitter channels on column I/O banks. Each I/O pair can be configured as a LVDS receiver or a LVDS transmitter. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If these pins are not used for differential signaling, these pins are available as user I/O pins. Connect unused pins as defined in the Intel® Quartus® Prime software.



These I/O banks are only available in the HF35 package of the GX 400 (1SG040), SX 400 (1ST040), and TX 400 (1SX040) devices. These pins support 1.2V, 1.25V, 1.35V, 1.5V, and 1.8V I/O standard. The LVDS, RSDS, and mini-LVDS I/O standards are only supported in the dedicated clock pin. The LVDS SERDES and EMIF functions are not supported in these I/O banks.

Bank 3D of the GX 400 (1SG040) and SX 400 (1SX040) devices in the HF35 package has a maximum of 30 I/O pins only.

Connect unused pins as defined in the Intel® Quartus® Prime software.