Intel® Stratix® 10 Device Family Pin Connection Guidelines

Download
ID 683028
Date 6/25/2022
Public
Document Table of Contents

External Memory Interface Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 7.  External Memory Interface Pins
Pin Name ( Intel® Stratix® 10 Devices) Pin Name ( Intel® Stratix® 10 GX 10M Device) Pin Functions Pin Description Connection Guidelines

DQS[0:47]

DQS[48:95]

DQS[0:47]

DQS[48:95]

I/O, bi-directional Optional data strobe signal for use in external memory interfacing. These pins drive to the dedicated DQS phase shift circuitry. Connect unused pins as defined in the Intel® Quartus® Prime software.

DQSn[0:47]

DQSn[48:95]

DQSn[0:47]

DQSn[48:95]

I/O, bi-directional Optional complementary data strobe signal for use in external memory interfacing. These pins drive to the dedicated DQS phase shift circuitry. Connect unused pins as defined in the Intel® Quartus® Prime software.

DQ[0:47]

DQ[48:95]

DQ[0:47]

DQ[48:95]

I/O, bi-directional Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important. However, if you plan on migrating to a different memory interface that has a different DQ bus width, you need to reevaluate your pin assignments. Analyze the available DQ pins across all pertinent DQS columns in the device pin-out file. Connect unused pins as defined in the Intel® Quartus® Prime software.

Did you find the information on this page useful?

Characters remaining:

Feedback Message