Intel® Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 6/25/2022
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HPS Oscillator Clock Input Pin

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 23.  HPS Oscillator Clock Input PinYou must provide one input clock source to the HPS.
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments
HPS_OSC_CLK

Clock input pin that drives the main PLL.

Connect a single-ended clock source to this pin. The I/O standard of the clock source must be compatible with VCCIO_HPS. For more information, refer to the valid frequency range of the clock source in the Intel® Stratix® 10 Device Datasheet.

Input Select one of the 48 HPS dedicated I/O in Platform Designer HPS Component.

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