Intel® Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 6/25/2022
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Example 17— Intel® Stratix® 10 TX (–2L and –3X parts)

Table 51.  Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–2L and –3X parts) with 15 Gbps < H-Tile Transceiver Data Rate <= 28.3 Gbps, and 10 Gbps < E-Tile Transceiver Data Rate <= 57.8 GbpsExample Requiring 9 Power Regulators
Power Pin Name Regulator Group Voltage Level (V) Supply Tolerance Power Source Regulator Sharing Notes
VCC 1

0.85

± 30mV Switcher (*) Share

Source VCC and VCCP from the same regulator, sharing the same voltage plane.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

VCCP
VCCERAM 2 0.9 ± 30mV Switcher (*) Share

Connect the VCCERAM to a dedicated 0.9V power supply. You have the option to connect VCCL_HPS to the same regulator as VCCERAM when the power rails require the same voltage level. You may connect the VCCPLLDIG_SDM and VCCPLLDIG_HPS power rails to the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel® Stratix® 10 TX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND.

VCCL_HPS
VCCPLLDIG_SDM Filter
VCCPLLDIG_HPS
VCCRT_GXE Filter

Connect VCCRT_GXE to VCCERAM through an LC filter. For more information about the LC filter design, refer to the Intel® Stratix® 10 Power Management User Guide.

VCCRTPLL_GXE Filter

You may source VCCRTPLL_GXE from the same regulator as VCCRT_GXE through a ferrite bead.

Filtering may be optional if this voltage rail can meet the noise mask requirement. For more information about the noise mask requirements, refer to the Intel® Stratix® 10 Power Management User Guide.

VCCR_GXB[L,R] 3 1.12 ± 20mV Switcher (*) Isolate

Connect the VCCR_GXB to a dedicated 1.12V power supply.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet.

VCCT_GXB[L,R] 4 1.12 ± 20mV Switcher (*) Isolate

Connect the VCCT_GXB to a dedicated 1.12V power supply.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet.

VCCH_GXE 5 1.1 ± 5% (**) Switcher (*) Isolate Connect the VCCH_GXE to a dedicated 1.1V power supply.
VCCCLK_GXE 6 2.5 ± 5% (**) Switcher (*) Isolate Connect VCCCLK_GXE to a dedicated 2.5V power supply.
VCCPT 7 1.8 ± 5% (**) Switcher (*) Share if 1.8V

You may source VCCPT and VCCBAT from the same regulator. You may connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices.

If you do not intend to utilize the HPS in the Intel® Stratix® 10 TX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND.

TX device,

When implementing a filtered supply topology, you must consider the IR drop across the filter.

VCCBAT Varies
VCCH_GXB[L,R] 1.8 Filter
VCCA_PLL 1.8
VCCPLL_SDM 1.8
VCCPLL_HPS 1.8
VCCADC 1.8
VCCIO_SDM 8 1.8 ± 5% (**) Switcher (*) Share if 1.8V You may source VCCIO_SDM, VCCIO, VCCIO3V, and VCCIO_HPS from the same regulator if they are at the same 1.8V voltage level.
VCCIO_HPS
VCCIO Varies
VCCIO3V
VCCFUSEWR_SDM 9 2.4 ± 50mV Switcher (*) Isolate Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND.

(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.

(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.

Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 TX device is provided in the following figure.

Figure 17. Example Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–2L and –3X parts) with 15 Gbps < H-Tile Transceiver Data Rate <= 28.3 Gbps, and 10 Gbps < E-Tile Transceiver Data Rate <= 57.8 Gbps

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