Intel® Stratix® 10 Device Family Pin Connection Guidelines

ID 683028
Date 6/25/2022
Document Table of Contents

Notes to Intel® Stratix® 10 Core Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.

Intel provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper device functionality.

  1. These pin connection guidelines are created based on the Intel® Stratix® 10 GX device variant.
  2. Select the capacitance values for the power supply after you consider the amount of power they need to supply over the frequency of operation of the particular circuit being decoupled. Calculate the target impedance for the power plane based on current draw and voltage drop requirements of the device/supply. Then, decouple the power plane using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Consider proper board design techniques such as interplane capacitance with low inductance for higher frequency decoupling. Refer to the PDN tool.
  3. Use the Intel® Stratix® 10 Early Power Estimator (EPE) to determine the preliminary current requirements for VCC and other power supplies. Use the Intel® Quartus® Prime Power Analyzer for the most accurate current requirements for this and other power supplies.
  4. These supplies may share power planes across multiple Intel® Stratix® 10 devices.
  5. Power pins should not share breakout vias from the BGA. Each ball on the BGA needs to have its own dedicated breakout via. VCC must not share breakout vias.
  6. Example 1 and Example 2 illustrate the power supply sharing guidelines for the Intel® Stratix® 10 GX devices.
  7. Low Noise Switching Regulator - defined as a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and other support components. The switching frequency is usually between 800kHz and 1MHz and has fast transient response. The switching frequency range is not an Intel requirement.
  8. The number of modular I/O banks on Intel® Stratix® 10 devices depends on the device density. For the indexes available for a specific device, please refer to the I/O Bank section in the Intel® Stratix® 10 General Purpose I/O User Guide.
  9. PCI Express protocol requires the AC-coupling capacitor to be placed on the transmitter side of the interface that permits adapters to be plugged and unplugged.
  10. Decoupling for these pins depends on the design decoupling requirements of the specific board.
  11. There are no dedicated PR_REQUEST, PR_ERROR, and PR_DONE pins. If required, you can use user I/O pins for these functions.
  12. The device orientation is die view (bottom of chip view).

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