Intel® Stratix® 10 Device Family Pin Connection Guidelines

ID 683028
Date 12/29/2023
Document Table of Contents

No Connect and DNU Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 11.  No Connect and DNU Pins
Pin Name ( Intel® Stratix® 10 Devices) Pin Name ( Intel® Stratix® 10 GX 10M Device) Pin Functions Pin Description Connection Guidelines
DNU DNU Do Not Use Do Not Use (DNU). Do not connect to power, GND, or any other signal. These pins must be left floating.
NC NC No Connect Do not drive signals into these pins.

When designing for device migration, you have the option to connect these pins to either power, GND, or a signal trace depending on the pin assignment of the devices selected for migration.

However, if device migration is not a concern, leave these pins floating.

The following guidelines are for the HF35 package of the Intel® Stratix® 10 GX 400 or Intel® Stratix® 10 SX 400 to Intel® Stratix® 10 GX 650 or Intel® Stratix® 10 SX 650 device migration:

  • You must tie the I/O pin that is incompatible for vertical migration to GND.
  • There are 48 I/O pins from bank 3C and 18 I/O pins from bank 3D that will be affected. You need to compare the device pin-outs and identify the affected pins.

For more information, refer to AN 921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package.