Intel® Stratix® 10 Device Family Pin Connection Guidelines

ID 683028
Date 12/29/2023
Document Table of Contents

Voltage Sensor Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 8.  Voltage Sensor Pins
Pin Name ( Intel® Stratix® 10 Devices) Pin Name ( Intel® Stratix® 10 GX 10M Device) Pin Functions Pin Description Connection Guidelines
VSIGP_[0,1] F[1,2]_VSIGP_[0,1] Input 2 pairs (for all Intel® Stratix® 10 FPGAs except Intel® Stratix® 10 GX 10M devices) or 4 pairs (for Intel® Stratix® 10 GX 10M device) of analog differential inputs pins used with the voltage sensor inside the FPGA to monitor external analog voltages.

Tie these pins to GND if you do not use the voltage sensor feature. For details on the usage of these pins, refer to the Intel® Stratix® 10 Analog to Digital Converter User Guide.

Do not drive VSIGP and VSIGN pins until the VCCADC power rail has reached 1.62V to prevent damage.

VSIGN_[0,1] F[1,2]_VSIGN_[0,1] Input