Intel® Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 12/29/2023
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Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Family Pin Connection Guidelines
Intel® Stratix® 10 Device Family Pin Connection Guidelines x
Intel® Stratix® 10 Core Pins Intel® Stratix® 10 High Bandwidth Memory (HBM) Pins H-Tile and L-Tile Pins Intel® Stratix® 10 E-Tile Pins Intel® Stratix® 10 P-Tile Pins Intel® Stratix® 10 Hard Processor System (HPS) Pins Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices Document Revision History for the Intel® Stratix® 10 Device Family Pin Connection Guidelines
Intel® Stratix® 10 Core Pins x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins 3V Compatible I/O Pins 3.3V I/O Pins Differential I/O Pins External Memory Interface Pins Voltage Sensor Pins Temperature Sensor Pins Reference Pins No Connect and DNU Pins Power Supply Pins Secure Device Manager (SDM) Pins Secure Device Manager (SDM) Optional Signal Pins Notes to Intel® Stratix® 10 Core Pins
Intel® Stratix® 10 High Bandwidth Memory (HBM) Pins x
UIB and eSRAM Pins Intel® Stratix® 10 HBM Power Supply Pins Notes to Intel® Stratix® 10 HBM Pins
H-Tile and L-Tile Pins x
H-Tile and L-Tile Pins
Intel® Stratix® 10 E-Tile Pins x
Intel® Stratix® 10 E-Tile Pins Notes to Intel® Stratix® 10 E-Tile Pins
Intel® Stratix® 10 P-Tile Pins x
Intel® Stratix® 10 P-Tile Power Supply Pins Intel® Stratix® 10 P-Tile Transceiver Pins
Intel® Stratix® 10 Hard Processor System (HPS) Pins x
HPS Supply Pins HPS Oscillator Clock Input Pin HPS JTAG Pins HPS GPIO Pins HPS SDMMC Pins HPS NAND Pins HPS USB Pins HPS EMAC Pins HPS I2C_EMAC and MDIO Pins HPS I2C Pins HPS SPI Pins HPS UART Pins HPS Trace Pins Notes to Intel® Stratix® 10 HPS Pins
Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices x
Example 1— Intel® Stratix® 10 GX Example 2— Intel® Stratix® 10 GX Example 3— Intel® Stratix® 10 GX (only for the HF35 Package) Example 4— Intel® Stratix® 10 GX (only for the HF35 Package) Example 5— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) Example 6— Intel® Stratix® 10 SX (–2L and –3X parts) Example 7— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) Example 8— Intel® Stratix® 10 SX (–2L and –3X parts) Example 9— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 10— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 11— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 12— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 13— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) Example 14— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) Example 15— Intel® Stratix® 10 MX (E-Tile) Example 16— Intel® Stratix® 10 TX (–1V, –2V, and –3V parts) Example 17— Intel® Stratix® 10 TX (–2L and –3X parts) Example 18— Intel® Stratix® 10 DX (–1V, –2V, and –3V parts) Example 19— Intel® Stratix® 10 GX 10M Example 20— Intel® Stratix® 10 GX 10M
Intel® Stratix® 10 Device Family Pin Connection Guidelines

UIB and eSRAM Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 15.  UIB and eSRAM Pins
Pin Name Pin Functions Pin Description Connection Guidelines
CLK_ESRAM_[0,1]p Embedded SRAM (eSRAM) Clock Input Dedicated positive high speed differential reference clock pin for eSRAM PLL.

Connect this pin to the positive terminal of an LVDS clock source within the range of 10 MHz to 325 MHz. The frequency selected must match the available options provided in the Intel® Quartus® Prime ESRAM PLL Reference Clock Frequency selection dialog box. Only DC-coupling is supported. The peak-to-peak jitter of this clock must meet or exceed the following jitter requirements for frequency bandwidth from 10 kHz to 1/2 of the frequency chosen:

  • 20 ps peak-to-peak
  • 1.42 ps RMS at 1e-12 BER
  • 1.22 ps at 1e-16 BER

Connect directly to GND if unused.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration.

CLK_ESRAM_[0,1]n eSRAM Clock Input Dedicated complement high speed differential reference clock pin for eSRAM PLL.

Connect this pin to the negative terminal of an LVDS clock source within the range of 10 MHz to 325 MHz. The frequency selected must match the available options provided in the Intel® Quartus® Prime ESRAM PLL Reference Clock Frequency selection dialog box. Only DC-coupling is supported. The peak-to-peak jitter of this clock must meet or exceed the following jitter requirements for frequency bandwidth from 10 kHz to 1/2 of the frequency chosen:

  • 20 ps peak-to-peak
  • 1.42 ps RMS at 1e-12 BER
  • 1.22 ps at 1e-16 BER

Connect directly to GND if unused.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration.

UIB_PLL_REF_CLK_[00,01]p UIB Clock Input Dedicated positive high speed differential reference clock pin for UIB PLL.

Connect this pin to the positive terminal of an LVDS clock source within the range of 10 MHz to 325 MHz. The frequency selected must match the available options provided in the Intel® Quartus® Prime HBM2 interface PLL Reference Clock Frequency selection dialog box. Only DC-coupling is supported. The peak-to-peak jitter of this clock must meet or exceed the following jitter requirements for frequency bandwidth from 10 kHz to 1/2 of the frequency chosen:

  • 20 ps peak-to-peak
  • 1.42 ps RMS at 1e-12 BER
  • 1.22 ps at 1e-16 BER

You must provide a stable reference clock to this pin before device configuration begins when the high-bandwidth memory (HBM2) IP is included in your design.

Connect directly to GND if unused.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration.

UIB_PLL_REF_CLK_[00,01]n UIB Clock Input Dedicated complement high speed differential reference clock pin for UIB PLL.

Connect this pin to the negative terminal of an LVDS clock source within the range of 10 MHz to 325 MHz. The frequency selected must match the available options provided in the Intel® Quartus® Prime HBM2 interface PLL Reference Clock Frequency selection dialog box. Only DC-coupling is supported. The peak-to-peak jitter of this clock must meet or exceed the following jitter requirements for frequency bandwidth from 10 kHz to 1/2 of the frequency chosen:

  • 20 ps peak-to-peak
  • 1.42 ps RMS at 1e-12 BER
  • 1.22 ps at 1e-16 BER

You must provide a stable reference clock to this pin before device configuration begins when the high-bandwidth memory (HBM2) IP is included in your design.

Connect directly to GND if unused.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration.

RREF_ESRAM_[0,1] eSRAM RREF Input Reference resistor pin for UIB PLL and eSRAM PLL, specific to top (T) and bottom (B) of device. If any UIB PLL or eSRAM PLL on the top or bottom side of the device is used, the corresponding RREF pin on that side of the device (top or bottom) must connect to its own individual 2K Ω +/-1% resistor to GND. The PCB trace between this pin and the reference resistor needs to be carefully routed to avoid any aggressor signals.
UIB_RREF_[00,01] UIB RREF Input Reference resistor pin for UIB IO ZQ calibration. Connect each pin through an individual 240Ω +/- 1% resistor to GND. No resistor sharing between pins is allowed. Leave this pin floating if unused.
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