3.3V I/O Pins
|Pin Name ( Intel® Stratix® 10 Devices)||Pin Name ( Intel® Stratix® 10 GX 10M Device)||Pin Functions||Pin Description||Connection Guidelines|
These are 3.3V I/O pins. The I/O bank is known as the 3.3V I/O bank and it is only available in the HF35 package of the GX400 (1SG040) and SX400 (1SX040) devices. These pins support 3.0V and 3.3V I/O.
The index of [5:0] represents the grouping of the I/O pins and the index of [7:0] represents the pin numbering within the same group. The I/O pin can be configured as an input or output within the same grouping index. When any of the pin within the same group is configured as an input or output, the remaining pins will be configured to the same I/O direction. The same I/O buffer setting such as the slew rate and weak pull-up functions will be applied for pins within the same grouping. Intel® recommends you to plan the I/O resources before implementing your design.
For more details about the supported I/O standards and features, refer to the Intel® Stratix® 10 General Purpose I/O User Guide.
Fore more details about the I/O electrical specification, refer to the Intel® Stratix® 10 Device Datasheet.
Connect these pins according to the I/O interface standard used in your design. To enable the 3.3V I/O bank, you must provide 3.0V or 3.3V power to VCCIO3C and 1.8V power to VCCIO3D. For unused I/O pins, leave the pins as NC.
Tie VREFB3CN0 to GND.
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