Intel® Stratix® 10 Device Family Pin Connection Guidelines

Download
ID 683028
Date 6/25/2022
Public
Document Table of Contents

Intel® Stratix® 10 P-Tile Pins

This section contains connection guidelines that are specific to the Intel® Stratix® 10 P-tile devices. The connection guidelines for the Intel® Stratix® 10 core pins are listed in the Intel® Stratix® 10 Core Pins section.
Note: You cannot change the P-tile IP for the PCI Express* ( PCIe* ) pin allocation in the Intel® Quartus® Prime project, but the P-tile IP for the PCIe* supports lane reversal and polarity inversion on the PCB.

Did you find the information on this page useful?

Characters remaining:

Feedback Message