Intel® Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 6/25/2022
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HPS Supply Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 22.  HPS Supply Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VCCL_HPS Power VCCL_HPS supplies power to the HPS core.

The VCCL_HPS power supply voltage could vary from 0.8V to 0.94V for –1V, –2V, or –3V devices with the SmartVID feature depending on the SmartVID setting in the device. When using –2L or –3X devices, you must connect to either 0.9V or 0.94V supply. If you are using 0.9V supply, VCCL_HPS can be connected to VCCERAM.

VCCL_HPS can be shared with VCC and VCCP if they are at the same voltage level only when using –1V, –2V, or –3V devices (with the SmartVID feature). VCCL_HPS cannot be shared with VCC and VCCP when using –2L or –3X devices. VCCL_HPS always needs to be equal to VCCPLLDIG_HPS.

Use the Intel® Stratix® 10 Early Power Estimator (EPE) and the Intel® Quartus® Prime Power Analyzer to determine the current requirements for VCCL_HPS and other power supplies.

Decoupling for these pins depends on the design decoupling requirements of the specific board.

See Notes 2, 3, 4, and 6 in Notes to Intel® Stratix® 10 HPS Pins.

If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave VCCL_HPS floating or connected to GND.

VCCIO_HPS Power The HPS dedicated I/Os support 1.8V voltage level.

Connect these pins to 1.8V power supply. If these pins have the same voltage requirement as VCCIO and VCCIO_SDM, you have the option to source VCCIO_HPS pins from the same regulator as VCCIO and VCCIO_SDM.

Decoupling for these pins depends on the design decoupling requirements of the specific board.

See Notes 2, 3, 4, and 8 in Notes to Intel® Stratix® 10 HPS Pins.

If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave VCCIO_HPS floating or connected to GND.

VCCPLL_HPS Power VCCPLL_HPS supplies analog power to the HPS PLLs.

Connect these pins to a 1.8V low noise power supply through a proper isolation filter. You have the option to share VCCPLL_HPS with the same regulator as VCCPT when all power rails require 1.8V but only with a proper isolation filter.

Decoupling for these pins depends on the design decoupling requirements of the specific board.

See Notes 2, 3, 4, and 7 in Notes to Intel® Stratix® 10 HPS Pins.

If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave VCCPLL_HPS floating or connected to GND.

VCCPLLDIG_HPS Power Digital power supply of the PLL in HPS.

Connect this to the VCCL_HPS with proper isolation filtering.

For more information about isolation filters, refer to AN583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs.

If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave VCCPLLDIG_HPS floating or connected to GND.

You can use the HPS Component in the Platform Designer to assign the HPS Dedicated I/Os to various HPS Peripherals and one hps_osc_clk input. The handoff files generated by the Platform Designer during the Intel® Quartus® Prime compilation will set the pin mux registers (pin0sel through pin47sel) and the HPS Oscillator Clock register (hps_osc_clk) to their respective HPS pin functions.

For more information about the valid combinations of the HPS I/O assignments, refer to the Hard Processor System Pin Information for Intel® Stratix® 10 Devices.

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