Intel® Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 6/25/2022
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Optional/Dual-Purpose Configuration Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 3.  Optional/Dual-Purpose Configuration Pins
Pin Name ( Intel® Stratix® 10 Devices) Pin Name ( Intel® Stratix® 10 GX 10M Device) Pin Functions Pin Description Connection Guidelines
AVST_DATA[31:0] I/O, Input

Dual-purpose configuration data input pins.

Use DATA [15:0] pins for Avalon Streaming Interface (Avalon-ST) x16 mode, DATA [31:0] pins for Avalon-ST x32 mode, or as regular I/O pins.

Avalon-ST x8 mode uses the SDM_IO pins.

These pins can also be used as user I/O pins after configuration.

If these pins are not used as the dual-purpose pins and they are not used as I/O pins, leave these pins unconnected.
AVST_CLK I/O, Input

Dual-purpose Avalon-ST interface clock input pin.

This pin is used for Avalon-ST x16 and x32 configuration schemes.

This pin can also be used as a user I/O pin after configuration.

Connect this pin to the clock signal of an external configuration controller when configuring using the Avalon-ST x16 or x32 interface.
AVST_VALID I/O, Input

Dual-purpose Avalon-ST interface data valid input pin.

This pin is used for Avalon-ST x16 and x32 configuration schemes.

This pin can also be used as a user I/O pin after configuration.

Connect this pin to the data valid signal of an external configuration controller when configuring using the Avalon-ST x16 or x32 interface.
nPERST[L,R][0:2] nPERST[L,R][0:2] I/O, Input

Dual-purpose fundamental reset pin that is only available when you use together with PCI Express® (PCIe®) hard IP (HIP).

When the PCIe HIP on a side (left or right) is enabled, the nPERST pins on that side cannot be used as general-purpose I/Os (GPIOs). In this case, connect the nPERST pin to the system PCIe nPERST signal to ensure that both ends of the link start link-training at the same time. The nPERST pins on a side are available as GPIOs only when the PCIe HIP on that side is not enabled.

When the pin is low, the transceivers are in reset. When the pin is high, the transceivers are out of reset. When you do not use this pin as the fundamental reset, you can use this pin as a user I/O pin.

Connect this pin as defined in the Intel® Quartus® Prime software. This pin is powered by the VCCIO3V supply.

When VCCIO3V is connected to a 3.0-V supply, you must use a diode to clamp the 3.3V LVTTL PCIe input signal to the VCCIO3V power of the device.

When VCCIO3V is connected to any voltage other than 3.0V, you must use a level translator to shift down the voltage from 3.3V LVTTL to the corresponding voltage level powering the VCCIO3V pin.

Only one nPERST pin is used per PCIe HIP. The Intel® Stratix® 10 components may have all six pins listed even when the specific component might only have 1 or 2 PCIe HIPs.
  • nPERSTL0 = Bottom Left PCIe HIP & CvP
  • nPERSTL1 = Middle Left PCIe HIP (When available)
  • nPERSTL2 = Top Left PCIe HIP (When available)
  • nPERSTR0 = Bottom Right PCIe HIP (When available)
  • nPERSTR1 = Middle Right PCIe HIP (When available)
  • nPERSTR2 = Top Right PCIe HIP (When available)

For maximum compatibility, always use the bottom left PCIe HIP first, as this is the only location that supports Configuration via Protocol (CvP) using the PCIe link.

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