Intel® Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 6/25/2022
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Clock and PLL Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 1.  Clock and PLL Pins
Pin Name ( Intel® Stratix® 10 Devices) Pin Name ( Intel® Stratix® 10 GX 10M Device) Pin Functions Pin Description Connection Guidelines

CLK_[2][A,B,C,F,G,H,I,J,K,L,M,N]_[0,1]p

CLK_[3][A,B,C,D,E,F,G,H,I,J,K,L]_[0,1]p

CLK_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_[0,1]p

CLK_[3] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_[0,1]p

I/O, Clock Input

Dedicated high speed clock input pins that can be used for data inputs or outputs. Differential input OCT Rd, single-ended input OCT Rt, and single-ended output OCT Rs are supported on these pins.

When you do not use these pins as dedicated clock pins, you can use them as regular I/O pins.

Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak internal pull-up resistor enabled, or as outputs driving GND.

CLK_[2][A,B,C,F,G,H,I,J,K,L,M,N]_[0,1]n

CLK_[3][A,B,C,D,E,F,G,H,I,J,K,L]_[0,1]n

CLK_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_[0,1]n

CLK_[3] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_[0,1]n

I/O, Clock Input

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_FB[0]

PLL_[3][A,B,C,F,G,H,I,J,K,L]_FB[0]

PLL_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_FB[0,1]

PLL_[3] [A,B,C,D,E,F,G,H,I,J,K,L]_U[1,2]_FB[0,1]

I/O, Clock

Dual-purpose I/O pins that can be used as single-ended inputs, single-ended outputs, or external feedback input pins.

For more information about the supported pins, refer to the device pin-out file.

Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak internal pull-up resistor enabled, or as outputs driving GND.

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_FBp

PLL_[3][A,B,C,F,G,H,I,J,K,L]_FBp

I/O, Clock

Dual-purpose I/O pins that can be used as differential I/Os, or external feedback input pins.

For more information about the supported pins, refer to the device pin-out file.

Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins.

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_FBn

PLL_[3][A,B,C,F,G,H,I,J,K,L]_FBn

I/O, Clock

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_CLKOUT[0:1]

PLL_[3][A,B,C,F,G,H,I,J,K,L]_CLKOUT[0:1]

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_CLKOUT[0:1]p

PLL_[3][A,B,C,F,G,H,I,J,K,L]_CLKOUT[0:1]p

PLL_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_CLKOUT[0:1]

PLL_[3] [A,B,C,D,E,F,G,H,I,J,K,L]_U[1,2]_CLKOUT[0:1]

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_CLKOUT[0:1]p

PLL_[2] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_CLKOUT[0:1]p
I/O, Clock

I/O pins that can be used as two single-ended clock output pins or one differential clock output pair.

For more information about the supported pins, refer to the device pin-out file.

Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak internal pull-up resistor enabled, or as outputs driving GND.

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_CLKOUT[0:1]n

PLL_[3][A,B,C,F,G,H,I,J,K,L]_CLKOUT[0:1]n

PLL_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_CLKOUT[0:1]n

PLL_[3] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_CLKOUT[0:1]n

I/O, Clock

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