Intel® Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 12/29/2023
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Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Family Pin Connection Guidelines
Intel® Stratix® 10 Device Family Pin Connection Guidelines x
Intel® Stratix® 10 Core Pins Intel® Stratix® 10 High Bandwidth Memory (HBM) Pins H-Tile and L-Tile Pins Intel® Stratix® 10 E-Tile Pins Intel® Stratix® 10 P-Tile Pins Intel® Stratix® 10 Hard Processor System (HPS) Pins Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices Document Revision History for the Intel® Stratix® 10 Device Family Pin Connection Guidelines
Intel® Stratix® 10 Core Pins x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins 3V Compatible I/O Pins 3.3V I/O Pins Differential I/O Pins External Memory Interface Pins Voltage Sensor Pins Temperature Sensor Pins Reference Pins No Connect and DNU Pins Power Supply Pins Secure Device Manager (SDM) Pins Secure Device Manager (SDM) Optional Signal Pins Notes to Intel® Stratix® 10 Core Pins
Intel® Stratix® 10 High Bandwidth Memory (HBM) Pins x
UIB and eSRAM Pins Intel® Stratix® 10 HBM Power Supply Pins Notes to Intel® Stratix® 10 HBM Pins
H-Tile and L-Tile Pins x
H-Tile and L-Tile Pins
Intel® Stratix® 10 E-Tile Pins x
Intel® Stratix® 10 E-Tile Pins Notes to Intel® Stratix® 10 E-Tile Pins
Intel® Stratix® 10 P-Tile Pins x
Intel® Stratix® 10 P-Tile Power Supply Pins Intel® Stratix® 10 P-Tile Transceiver Pins
Intel® Stratix® 10 Hard Processor System (HPS) Pins x
HPS Supply Pins HPS Oscillator Clock Input Pin HPS JTAG Pins HPS GPIO Pins HPS SDMMC Pins HPS NAND Pins HPS USB Pins HPS EMAC Pins HPS I2C_EMAC and MDIO Pins HPS I2C Pins HPS SPI Pins HPS UART Pins HPS Trace Pins Notes to Intel® Stratix® 10 HPS Pins
Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices x
Example 1— Intel® Stratix® 10 GX Example 2— Intel® Stratix® 10 GX Example 3— Intel® Stratix® 10 GX (only for the HF35 Package) Example 4— Intel® Stratix® 10 GX (only for the HF35 Package) Example 5— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) Example 6— Intel® Stratix® 10 SX (–2L and –3X parts) Example 7— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) Example 8— Intel® Stratix® 10 SX (–2L and –3X parts) Example 9— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 10— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 11— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 12— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 13— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) Example 14— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) Example 15— Intel® Stratix® 10 MX (E-Tile) Example 16— Intel® Stratix® 10 TX (–1V, –2V, and –3V parts) Example 17— Intel® Stratix® 10 TX (–2L and –3X parts) Example 18— Intel® Stratix® 10 DX (–1V, –2V, and –3V parts) Example 19— Intel® Stratix® 10 GX 10M Example 20— Intel® Stratix® 10 GX 10M
Intel® Stratix® 10 Device Family Pin Connection Guidelines

Intel® Stratix® 10 P-Tile Power Supply Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 20.   Intel® Stratix® 10 P-Tile Power Supply Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VCCH_GXP[L, R][1, 2, 3] Power Secondary high-voltage analog supply for transceivers and on-die PLL specific to P-tile.

Connect VCCH_GXP to a 1.8V low-noise switching regulator. Place a 22–nF decoupling capacitor between each VCCH_GXP power pin and GND pin on the back side of the BGA pin field.

VCCH_GXP must be filtered through the ferrite bead.

VCCH_GXP must be powered up even when the P-tile transceivers are not used.

VCCRT_GXP[L, R][1, 2, 3] Power Primary analog supply for the TX and RX channels, specific to P-tile.

Connect VCCRT_GXP to a 0.9V low-noise switching regulator. With a proper isolation filtering, you have the option to source VCCRT_GXP from the same regulator as VCCERAM.

VCCRT_GXP must be powered up even when the P-tile transceivers are not used.

VCCCLK_GXP[L, R][1, 2, 3] Power LVCMOS I/O buffer supply rail, specific to P-tile.

Connect VCCCLK_GXP to a 1.8V low-noise switching regulator. With a proper isolation filtering, you have the option to source VCCCLK_GXP from the same regulator as VCCPT.

VCCCLK_GXP must be powered up even when the P-tile transceivers are not used.

VCCFUSE_GXP Power Required power supply for the firmware to read internal settings for the one-time programmable eFuses.

Connect the VCCFUSE_GXP pin to the 0.9V VCCERAM power. Connecting to the VCCERAM power rail adheres to the power-down sequencing requirement for the VCCFUSE_GXP supply. Do not leave this pin floating or tie it to GND.

VCCFUSE_GXP must be powered up even when the P-tile transceivers are not used.

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