Visible to Intel only — GUID: ici1484644390828
Ixiasoft
Visible to Intel only — GUID: ici1484644390828
Ixiasoft
3V Compatible I/O Pins
Pin Name ( Intel® Stratix® 10 Devices) | Pin Name ( Intel® Stratix® 10 GX 10M Device) | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|---|
IO3V[0,1,2,3,4,5,6,7]_[10,12,20,22] | T[1,2,3,4]_IO3V[0,1,2,3,4,5,6,7] | I/O | These are the 3.0V I/O pins. Each H- or L- transceiver tile supports eight 3.0V I/O pins. These pins support 1.2V, 1.25V, 1.35V, 1.5V, 1.8V, 2.5V, and 3.0V I/O standards. For details about the supported I/O standards, refer to the Intel® Stratix® 10 Device Datasheet. |
Connect these pins according to the I/O interface standard you are using. You must provide power to the VCCR_GXB, VCCT_GXB, and VCCH_GXB pins of a transceiver tile to enable the 3.0V I/O pins within that tile. For any transceiver tiles that have their VCCR_GXB, VCCT_GXB, and VCCH_GXB unpowered, the corresponding 3.0V I/O pins within that tile is disabled. Using 3V I/O pins from an unpowered tile can potentially result in configuration failures. Connect unused pins as defined in the Intel® Quartus® Prime software. |
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