Ethernet Support Center

Welcome to the Ethernet IP Support Center!

Here you will find information on how to select, design, and implement Ethernet links. There are also guidelines on how to bring up your system and debug the Ethernet links. This page is organized into categories that align with an Ethernet system design flow from start to finish.

Enjoy your journey!

Get support resources for Intel® Agilex™, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation Archive, Training Courses, Videos and Webcasts, Design Examples, and Knowledge Base.

Getting Started

1. Device and IP Selection

Which Intel® FPGA Family Should I Use?

Refer to Table 1 to understand the Ethernet intellectual property (IP) core support for Intel Agilex, Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 devices. Compare between the four devices to select the right device for your Ethernet subsystem implementation.

Table 1 - Device and IP Core Support

Device Family

Tile Type (Intel® Agilex™ device only)

IP Core

Electrical Interface

Forward Error Correction

1588 Precision Time Protocol

Auto Negotiation/ Link Training

Intel® Agilex

E-Tile

E-Tile Hard IP for Ethernet Intel FPGA IP User Guide (HTML | PDF)

E-Tile Hard IP for Ethernet Intel Agilex FPGA IP Design Example User Guide

(HTML | PDF)

100GBASE-KR4 100GBASE-CR4

CAUI-4 CAUI-2

25GBASE-KR 25GBASE-CR

25GBASE-R AUI 

25GBASE-R Consortium Link

10GBASE-KR 10GBASE-CR

Reed Solomon (528, 514)

Reed Solomon (544, 514)

F-Tile

Upcoming with F-Tile public release

TBD

TBD

TBD

TBD

Device Family

Tile Type (Intel® Stratix® 10 device only)

IP Core

Electrical Interface

Forward Error Correction

1588 Precision Time Protocol

Auto Negotiation/ Link Training

Intel® Stratix® 10 GX/SX/MX/TX/DX

L-Tile and H-Tile

Triple Speed Ethernet Intel® FPGA IP
View IP core user guide (HTML | PDF)

10BASE-T 100BASET 1000BASE-T 1000BASE-X

 

L-Tile and H-TIle

Low Latency Ethernet 10G MAC Intel FPGA IP
View IP core user guide (HTML | PDF)
View design example user guide (HTML | PDF)

10BASE-T 100BASET 1000BASE-T 1000BASE-X 10GBASE-R NBASE-T MGBASE-T

Firecode FEC

L-Tile and H-Tile

10GBASE-R Intel FPGA IP
View IP core user guide for L- and H-tile (HTML | PDF)

L-Tile and H-Tile

10GBASE-KR PHY Intel FPGA IP
View IP core user guide (HTML | PDF)

L-Tile and H-Tile

1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP
View IP core user guide (HTML | PDF)

L-Tile and H-Tile

Low Latency 40-Gbps Ethernet Intel FPGA IP
View IP core user guide (HTML | PDF)
View design example user guide (HTML | PDF)

40G-BASE-R4

Firecode FEC

 

H-Tile

Intel® FPGA H-Tile Hard IP for Ethernet

View IP core user guide (HTML | PDF)
View design example user guide (HTML | PDF)

50G-BASE-R2

100G-BASE-R4

 

 

L-Tile and H-Tile

25G Ethernet Intel Stratix 10 FPGA IP

View IP core user guide (HTML | PDF)
View design example user guide (HTML | PDF)

25GBASE-SR

10GBASE-R

Reed Solomon (528, 514)

 

L-Tile and H-Tile

Low Latency 100-Gbps Ethernet Intel FPGA IP
View IP core user guide (HTML | PDF)
View design example user guide (HTML | PDF)

100G-BASE-R4

Reed Solomon (528, 514)

 

 

E-Tile

E-Tile Hard IP for Ethernet Intel FPGA IP User Guide (HTML | PDF)

E-Tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Design Example User Guide

(HTML | PDF)

100GBASE-KR4 100GBASE-CR4

CAUI-4 CAUI-2

25GBASE-KR 25GBASE-CR

25GBASE-R AUI 

25GBASE-R Consortium Link

10GBASE-KR 10GBASE-CR

Reed Solomon (528, 514)

Reed Solomon (544, 514)

Device Family

IP Core

Electrical Interface

Forward Error Correction

1588 Precision Time Protocol

Auto Negotiation/ Link Training

Intel® Arria® 10 GX/GT/SX

Triple Speed Ethernet Intel FPGA IP
View IP core user guide (HTML | PDF)

10BASE-T 100BASET 1000BASE-T 1000BASE-X

 

Low Latency Ethernet 10G MAC Intel FPGA IP
View IP core user guide (HTML | PDF)
View design example user guide (HTML | PDF)

10BASE-T 100BASET 1000BASE-T 1000BASE-X 10GBASE-R NBASE-T MGBASE-T

Firecode FEC

10GBASE-R Intel FPGA IP
View IP core user guide (HTML | PDF)

XAUI PHY Intel FPGA IP
View IP core user guide (HTML | PDF)

1G/10GbE and 10GBASE-KR PHY Intel FPGA IP
View IP core user guide (HTML | PDF)

1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP
View IP core user guide (HTML | PDF)

Low Latency 40 Gbps Ethernet Intel FPGA IP

View IP core user guide (HTML | PDF)

View design example user guide (HTML | PDF)

40G-BASE-R4

Firecode FEC

Low Latency 100 Gbps Ethernet Intel FPGA IP
View IP core user guide (HTML | PDF)
View design example user guide (HTML | PDF)

100G-BASE-R10 100G-BASE-R4

Reed Solomon (528, 514)

 

25 Gbps Ethernet Intel FPGA IP
View IP core user guide (HTML | PDF)
View design example user guide (HTML | PDF)

25G-BASE-R1

Reed Solomon (528, 514)

 

50 Gbps Ethernet Intel FPGA IP
View IP core user guide (HTML | PDF)
View design example user guide (HTML | PDF)

50G-BASE-R2

 

 

 

Device Family

IP Core

Electrical Interface

Forward Error Correction

1588 Precision Time Protocol

Auto Negotiation/ Link Training

Intel® Cyclone® 10 LP/GX

Triple Speed Ethernet Intel FPGA IP
View IP core user guide (HTML | PDF)

10BASE-T 100BASET 1000BASE-T 1000BASE-X

 

Low Latency Ethernet 10G MAC Intel FPGA IP

(Intel Cyclone® 10 GX only)
View IP core user guide (HTML | PDF)

10GBASE-R

 

 

Please refer to the respective user guides to understand and find out whether the various features listed in the table above are mutually exclusive. For example: Intel FPGA IP for Low Latency 100 Gbps Ethernet (for Intel Arria 10 devices) does not allow you to enable the RS-FEC and 1588 PTP simultaneously.

2. Design Flow and IP Integration

Where Can I Find Information on IP Integration?

Refer to the Getting Started section of your chosen IP core user guide. You can also refer to the following documents for details:

Intel Arria 10 Devices

  • AN 735: Intel® FPGA Low Latency Ethernet 10G MAC IP Core Migration Guidelines (HTML | PDF)
  • AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC IP Core in Arria® 10 Devices (HTML | PDF)
  • AN 808: Migrating Guidelines from Intel Arria® 10 to Intel Stratix® 10 for 10G Ethernet Subsystem (HTML | PDF)

Intel Stratix 10 Devices

  • AN 778: Intel Stratix 10 Transceiver Usage (HTML | PDF)

Intel Agilex Devices

  • Intel Agilex General Purpose I/O and LVDS SERDES User Guide (HTML | PDF)
  • Intel Agilex Configuration User Guide (HTML | PDF)

Which Ethernet IP Core Should I Use?

Intel® FPGA IP for Ethernet

The Intel FPGA IP for Ethernet portfolio contains various IP types to support data rates from 10 Mbps to 100 Gbps. Ethernet IP solutions encompass the Media Access Controller and PHY IP core, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). For more information, refer to the following user guides:

Intel Agilex Devices

  • Intel® E-Tile Hard IP for Ethernet Intel FPGA IP User Guide (HTML | PDF)
  • Intel E-Tile Transceiver PHY User Guide (HTML | PDF)
  • Intel E-Tile Channel Placement Tool DOWNLOAD
  • Intel Agilex Device Datasheet (HTML | PDF)

Intel Stratix 10 Devices

  • Intel FPGA Triple Speed Ethernet IP Core User Guide (HTML | PDF)
  • Intel FPGA Low Latency Ethernet 10G MAC IP Core User Guide (HTML | PDF)
  • Intel Stratix 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core User Guide (HTML | PDF)
  • Intel Stratix 10 10GBASE-KR PHY IP Core User Guide (HTML | PDF)
  • Intel Stratix 10 Low Latency 40-Gbps Ethernet IP Core User Guide (HTML | PDF)
  • Intel Stratix 10 Low Latency 100-Gbps Ethernet IP Core User Guide (HTML | PDF)
  • Intel Stratix 10 E-Tile Hard IP for Ethernet Intel FPGA IP User Guide (HTML | PDF)
  • Intel Stratix 10 E-Tile Transceiver PHY User Guide (HTML | PDF)
  • Intel Stratix 10 H-Tile Hard IP for Ethernet Intel FPGA IP User Guide (HTML | PDF)
  • Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide (HTML | PDF)
  • Intel Stratix 10 Device Datasheet (HTML | PDF)
  • Intel E-Tile Channel Placement Tool DOWNLOAD

Intel Arria 10 Devices

  • Intel FPGA Triple Speed Ethernet IP Core User Guide (HTML | PDF)
  • Intel FPGA Low Latency Ethernet 10G MAC IP Core User Guide (HTML | PDF)
  • 25 Gbps Ethernet IP Core User Guide (HTML | PDF)
  • 50 Gbps Ethernet IP Core User Guide (HTML | PDF)
  • Low Latency 40 Gbps Ethernet IP Core User Guide (HTML | PDF)
  • Low Latency 100 Gbps Ethernet IP Core User Guide (HTML | PDF)
  • Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide (HTML | PDF)

Intel Cyclone 10 Devices

  • Intel FPGA Triple Speed Ethernet IP Core User Guide (HTML | PDF)
  • Intel FPGA Low Latency Ethernet 10G MAC IP Core User Guide (HTML | PDF)

3. Board Design and Power Management

Pin Connection Guidelines

Intel Cyclone 10 Devices

  • Intel Cyclone 10 GX Device Family Pin Connection Guidelines (HTML | PDF)

Intel Arria 10 Devices

  • Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines (HTML | PDF)

Intel Stratix 10 Devices

  • Intel Stratix 10 GX, MX, TX, DX, and SX Device Family Pin Connection Guidelines (HTML | PDF)

Intel Agilex Devices

  • Intel Agilex Device Family Pin Connection Guidelines (HTML | PDF)

Board Design Guidelines

  • Board Layout Test
  • AN 114: Board Design Guidelines for Intel® Programmable Device Packages (HTML | PDF)
  • AN 766: Intel Stratix 10 Devices, High-Speed Signal Interface Layout Design Guideline (HTML | PDF)
  • AN 613: PCB Stackup Design Considerations for Intel FPGAs (HTML | PDF)
  • AN 875: Intel Stratix 10 E-Tile PCB Design Guidelines (HTML | PDF)
  • AN 886: Intel Agilex Device Design Guidelines (HTML | PDF)
  • Intel Agilex Power Management User Guide (HTML | PDF)
  • Intel Agilex Device Family High-Speed Serial Interface Signal Integrity Design Guidelines (HTML | PDF)
  • AN 910: Intel Agilex Power Distribution Network Design Guidelines (HTML | PDF)

Early Power Estimator

Thermal Power Guidelines

  • AN 787: Intel Stratix 10 Thermal Modeling and Management (HTML | PDF)

Power Sequencing Guidelines

  • AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Devices (HTML | PDF)

4. Design Examples and Reference Designs

Design Examples and Reference Designs

Intel Arria 10 Devices

Intel Stratix 10 Devices

  • Triple-Speed Ethernet
  • AN830: Intel FPGA Triple Speed Ethernet and On Board PHY Chip Reference Design (HTML | PDF)
  • 1G/2.5G Ethernet
  • 1G/2.5G Ethernet Design Example for Intel Stratix 10
  • 10G Ethernet
  • Intel FPGA IP for Low Latency Ethernet 10G MAC design example user guide (HTML | PDF)
  • 40G Ethernet
  • Intel FPGA IP for Low Latency 40-Gbps Ethernet design example user guide (HTML | PDF)
  • Intel FPGA H-Tile Hard IP for Ethernet
  • Design example user guide (HTML | PDF)
  • 100G Ethernet
  • Intel FPGA IP for Low Latency 100-Gbps Ethernet design example user guide (HTML | PDF)
  • E-Tile Hard IP for Ethernet Intel Stratix 10
  • FPGA IP Design Example User Guide (HTML | PDF)

Intel Agilex Devices

  • E-Tile Hard IP for Ethernet Intel Agilex Devices
  • FPGA IP Design Example User Guide (HTML | PDF)

5. Training Courses and Videos

Training Courses

Ethernet Training Courses

Videos

Title

Description

How Intel FPGA 1588 System Solution Work in Different Clock Mode

Learn about Intel's new 1588 system-level reference design using both the Intel FPGA IP for 10G Ethernet MAC with 10G BaseR PHY and software, which includes the PTP stack LinuxPTPv1.5, a preloader, a 10 Gbps Ethernet MAC driver, and a PTP driver.

Debug Techniques for an Intel FPGA Nios® II Ethernet Design - Part 1

Learn about debugging techniques for Ethernet or Nios II processor designs.

Debug Techniques for an Intel FPGA Nios II Ethernet Design - Part 2

Learn about debugging techniques for Ethernet or Nios II processor designs.

How to Debug Intel FPGA Triple Speed Ethernet Auto Negotiation Issue

Learn how to use auto negotiation for synchronizing Ethernet peripherals.

How to Debug TSE Auto-Negotiation Issue

Learn how to debug triple-speed Ethernet link synchronization issues.

How to Migrate Intel FPGA Triple Speed Ethernet to Arria 10 Devices in Quartus® Software

Learn how to migrate IP cores to the Intel Arria 10 FPGA family using the Intel FPGA IP for Triple-Speed Ethernet as an example.

Migration from legacy 10G Ethernet MAC IP to the new low latency 10G Ethernet MAC IP

Learn about the Intel FPGA IP for Low Latency 10G Ethernet MAC and how to migrate from the legacy Intel FPGA IP for 10G Ethernet MAC.

Networking Features Under UEFI Shell

Learn how to use the Ethernet features under the UEFI Shell after booting to the DXE phase.

Scalable 10G MAC + 1G/10G PHY with 1588 Design Example Hardware Demo

Watch a demonstration on the Intel FPGA IP for 10G Ethernet MAC and the Intel® FPGA IP for 1G/10G PHY with the IEEE 1588 feature. Learn how to perform the design hardware test and how to modify the hardware tcl script to specify the purpose of the test.

Intel 2.5G Ethernet IP

Watch the 2.5G Ethernet IP Chalk Talk video

Other Videos

6. Debug

Tools

Intel Stratix 10 Device Ethernet Link Inspector

Ethernet Link Inspector consists of two sub-tools:

  1. Link Monitor - Allows you to continuously monitor health of Ethernet link(s) between Intel Stratix 10 device and the link partner. Some of the key features you can monitor are: Link status summary (CDR lock, RX recovered frequency, lane alignment lock etc..) MAC packet statistics, FEC statistics etc.
  2.  Link Analysis - Allows you to have transparency into the link bring up sequence (like Auto-negotiation, Link Training etc.) or any other event captured in the Signal Tap Logic Analyzer file. Configure & capture the Signal Tap Logic Analyzer file for given event and then use Link Analysis to import the captured event & study Intel Stratix 10 behavior during that event duration.

To access Ethernet Link Inspector for a specific Intel® Quartus® software version, please refer to the table below.

  • For IP and Device support use model, refer to section ‘1.2 Supported IP Cores and Devices’ in the relevant Ethernet Link Inspector user guide.

Tool Files

Intel Quartus Software Version

User Guide

Intel Stratix 10 Ethernet Link Inspector STP Package for Intel Quartus Prime 19.1 Pro (this tool is integrated into Quartus 19.1+)

Intel Quartus software 19.1 and above (L, H, and E-Tiles)

Intel Stratix 10 Ethernet Link Inspector User Guide for Quartus Prime 19.1 Pro

Ethernet Link Inspector Package v4.1

Intel Quartus software 18.0 to 18.1.2 (L, H, and E-Tiles)

Ethernet Link Inspector User Guide v4.1 for Intel Stratix 10 Devices

Ethernet Link Inspector Package v1.1

Intel Quartus software 17.1 and earlier (L and H-Tiles)

Ethernet Link Inspector User Guide v1.1 for Intel Stratix 10 Devices

Intellectual Property (IP) Core Release Notes

Intel Cyclone 10 Devices

  • Intel FPGA Triple Speed Ethernet IP Core Release Notes (HTML | PDF)
  • Intel FPGA Low Latency Ethernet 10G MAC IP Core Release Notes (HTML | PDF)

Intel Arria 10 Devices

  • Intel FPGA Triple Speed Ethernet IP Core Release Notes (HTML | PDF)
  • Intel FPGA Low Latency Ethernet 10G MAC IP Core Release Notes (HTML | PDF)
  • 1G/10G and Backplane Ethernet 10GBASE-KR PHY Release Notes (HTML | PDF)
  • 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Release Notes (HTML | PDF)
  • 25G Ethernet IP Core Release Notes (HTML | PDF)
  • Low Latency 40Gbps Ethernet IP Core Release Notes (HTML | PDF)
  • Low Latency 100-Gbps Ethernet IP Core Release Notes (HTML | PDF)

Intel Stratix 10 Devices

  • Intel FPGA Triple Speed Ethernet IP Core Release Notes (HTML | PDF)
  • Intel FPGA Low Latency Ethernet 10G MAC IP Core Release Notes (HTML | PDF)
  • Intel Stratix 10 10GBASE-KR PHY Release Notes (HTML | PDF)
  • Intel Stratix 10 H-Tile Hard IP for Ethernet IP Core Release Notes (HTML | PDF)
  • Intel Stratix 10 Low Latency 40-Gbps Ethernet IP Core Release Notes (HTML | PDF)
  • Intel Stratix 10 Low Latency 100-Gbps Ethernet IP Core Release Notes (HTML | PDF)
  • Intel Stratix 10 E-Tile Hard IP for Ethernet Intel FPGA IP Release Notes (HTML | PDF)

Intel Agilex Devices

  • Intel Agilex E-Tile Hard IP for Ethernet Intel FPGA IP Release Notes (HTML | PDF)

Still Have Questions?