Ethernet Support Center

The Ethernet IP Support Center provides information on how to select, design, and implement Ethernet links for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10, and Cyclone® 10 devices. There are also guidelines on how to bring up your system and debug the Ethernet links. This page is organized into categories that align with an Ethernet system design flow from start to finish.

Get additional support for Agilex™ 7 FPGA Interface Protocol Design, Agilex™ 5 FPGA Interface Protocol Design, and Agilex™ 3 FPGA Interface Protocol Design step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation.

For other devices, search the Device and Product Support Collections.

Getting Started

Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

Agilex™ 7 Device Schematic Review Worksheet

Agilex™ 5 FPGAs and SoCs PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN)

Agilex™ 5 Device Schematic Review Worksheet

PCB Layout, Routing, and Power Distribution Network Design Guidelines: Agilex™ 3 FPGAs and SoCs

1. Device and IP Selection

Which FPGA Family Should I Use?

Refer to Table 1 to understand the Ethernet intellectual property (IP) core support for Agilex™, Stratix® 10, Arria® 10, and Cyclone® 10 devices. Compare between the four devices to select the right device for your Ethernet subsystem implementation.

Please refer to the respective user guides to understand and find out whether the various features listed in the table above are mutually exclusive. For example: FPGA IP for Low Latency 100 Gbps Ethernet (for Arria® 10 devices) does not allow you to enable the RS-FEC and 1588 PTP simultaneously.

2. Design Flow and IP Integration

Where Can I Find Information on IP Integration?

Refer to the Getting Started section of your chosen IP core user guide. You can also refer to the following documents for details:

Agilex™ Devices

• Agilex™ 7 F-Series and I-Series General-Purpose I/O User Guide
• Agilex™ 7 Configuration User Guide
• Agilex™ 5 FPGAs and SoCs General-Purpose I/O User Guide
• Agilex™ 5 Configuration User Guide
• Agilex™ 3 FPGAs and SoCs General-Purpose I/O User Guide

Stratix® 10 Devices

• AN 778: Stratix® 10 Transceiver Usage

Arria® 10 Devices

• AN 735: FPGA Low Latency Ethernet 10G MAC IP Core Migration Guidelines
• AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC IP Core in Arria® 10 Devices
• AN 808: Migrating Guidelines from Arria® 10 to Stratix® 10 for 10G Ethernet Subsystem

Which Ethernet IP Core Should I Use?

FPGA IP for Ethernet

The FPGA IP for Ethernet portfolio contains various IP types to support data rates from 10 Mbps to 100 Gbps. Ethernet IP solutions encompass the Media Access Controller and PHY IP core, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). For more information, refer to the following user guides:

Agilex™ Devices

• E-Tile Hard IP for Ethernet FPGA IP User Guide
• E-Tile Transceiver PHY User Guide
• E-Tile Channel Placement Tool
• Agilex™ 7 Device Data Sheet
• Agilex™ 5 Device Data Sheet
• Agilex™ 3 Device Data Sheet

Stratix® 10 Devices

• FPGA Triple Speed Ethernet IP Core User Guide
• FPGA Low Latency Ethernet 10G MAC IP Core User Guide
• Stratix® 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core User Guide
• Stratix® 10 10GBASE-KR PHY IP Core User Guide
• Stratix® 10 Low Latency 40-Gbps Ethernet IP Core User Guide
• Stratix® 10 Low Latency 100-Gbps Ethernet IP Core User Guide
• Stratix® 10 E-Tile Hard IP for Ethernet FPGA IP User Guide
• Stratix® 10 E-Tile Transceiver PHY User Guide
• Stratix® 10 H-Tile Hard IP for Ethernet FPGA IP User Guide
• Stratix® 10 L- and H-Tile Transceiver PHY User Guide
• Stratix® 10 Device Datasheet
• E-Tile Channel Placement Tool

Arria® 10 Devices

• FPGA Triple Speed Ethernet IP Core User Guide
• FPGA Low Latency Ethernet 10G MAC IP Core User Guide
• 25 Gbps Ethernet IP Core User Guide
• 50 Gbps Ethernet IP Core User Guide
• Low Latency 40 Gbps Ethernet IP Core User Guide
• Low Latency 100 Gbps Ethernet IP Core User Guide
• Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

Cyclone® 10 Devices

• FPGA Triple Speed Ethernet IP Core User Guide
• FPGA Low Latency Ethernet 10G MAC IP Core User Guide

3. Board Design and Power Management

Pin Connection Guidelines

Agilex™ Devices

• Agilex™ 7 Device Family Pin Connection Guidelines
• Agilex™ 5 Device Family Pin Connection Guidelines
• Agilex™ 3 Device Family Pin Connection Guidelines

Stratix® 10 Devices

• Stratix® 10 GX, MX, TX, DX, and SX Device Family Pin Connection Guidelines

Arria® 10 Devices

• Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

Cyclone® 10 Devices

• Cyclone® 10 GX Device Family Pin Connection Guidelines

Schematic Review

Agilex™ Devices

• Agilex™ 7 Device Schematic Review Worksheet
• Agilex™ 5 Device Schematic Review Worksheet

Stratix® 10 Devices

• Stratix® 10 GX, MX, TX and SX Schematic Review Worksheet

Arria® 10 Devices

• Arria® 10 GX, GT, and SX Schematic Review Worksheet

Cyclone® 10 Devices

• Cyclone® 10 GX Schematic Review Worksheet

Board Design Guidelines

• AN 886: Agilex™ 7 Device Design Guidelines
• Agilex™ 7 Power Management User Guide
• Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines
• AN 910: Agilex™ 7 Power Distribution Network Design Guidelines
• Agilex™ 5 Power Management User Guide
• Agilex™ 5 FPGAs and SoCs PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN)
• Agilex™ 5 Power Distribution Network Design Guidelines
• Agilex™ 3 FPGAs and SoC Device Design Guidelines
• Board Layout Test
• AN 766: Stratix® 10 Devices, High-Speed Signal Interface Layout Design Guideline
• AN 875: Stratix® 10 E-Tile PCB Design Guidelines
• AN 114: Board Design Guidelines for Programmable Device Packages
• AN 613: PCB Stackup Design Considerations for FPGAs

Early Power Estimator

• Early Power Estimator (EPE) and Power Analyzer
• AN 750: Using the FPGA PDN Tool to Optimize Your Power Delivery Network Design
• Device-Specific Power Deliver Network (PDN) Tool 2.0 User Guide

Thermal Power Guidelines

• AN 787: Stratix® 10 Thermal Modeling and Management

Power Sequencing Guidelines

• AN 692: Power Sequencing Considerations for Agilex™ 7, Stratix® 10, Arria® 10 and Cyclone® 10 GX Devices

4. Design Examples and Reference Designs

Agilex™ 7 Devices

• E-Tile Hard IP for Ethernet Agilex™ Devices
  • FPGA IP Design Example User Guide
• Triple-Speed Ethernet IP
• F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide
• 10G Ethernet IP
  • F-Tile Low Latency Ethernet 10G MAC FPGA IP Design Example User Guide
• 25G Ethernet IP
  • F-Tile 25G Ethernet FPGA IP Design Example User Guide
• F-Tile Ethernet Hard IP
  • F-Tile Ethernet FPGA Hard IP Design Example User Guide
  • F-Tile Dynamic Reconfiguration Design Example User Guide

Stratix® 10 Devices

• Triple-Speed Ethernet
  • AN830: FPGA Triple Speed Ethernet and On Board PHY Chip Reference Design
• 1G/2.5G Ethernet
  • 1G/2.5G Ethernet Design Example for Stratix® 10
• 10G Ethernet
  • FPGA IP for Low Latency Ethernet 10G MAC design example user guide
• 40G Ethernet
  • FPGA IP for Low Latency 40-Gbps Ethernet design example user guide
• FPGA H-Tile Hard IP for Ethernet
  • Design example user guide
• 100G Ethernet
  • FPGA IP for Low Latency 100-Gbps Ethernet design example user guide
• E-Tile Hard IP for Ethernet Stratix® 10
  • FPGA IP Design Example User Guide

Arria® 10 Devices

• Triple-Speed Ethernet
  • AN647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design
  • AN-744: Scalable Triple Speed Ethernet Reference Design for Arria® 10 Devices
  • Arria® 10 Triple Speed Ethernet and Native PHY Design Example
  • Arria® 10 Triple Speed Ethernet with IEEE 1588v2 and Native PHY Design Example
• 10G Ethernet
  • AN 699: Using the FPGA Ethernet Design Toolkit
  • AN794: Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
  • AN 701: Scalable Low Latency Ethernet 10G MAC using Arria® 10 1G/10G PHY
  • AN 838: Interoperability between Arria® 10 NBASE-T Ethernet Solution with Aquantia Ethernet PHY Reference Design
  • Arria® 10 SoC Scalable Multi-speed 10M-10G Ethernet Design Example
  • Arria® 10 Scalable 10G Ethernet MAC + Native PHY with IEEE 1588v2 Design Example

5. Debug

Tools

Stratix® 10 Device Ethernet Link Inspector

Ethernet Link Inspector consists of two sub-tools:

1. Link Monitor - Allows you to continuously monitor health of Ethernet link(s) between Stratix® 10 device and the link partner. Some of the key features you can monitor are: Link status summary (CDR lock, RX recovered frequency, lane alignment lock etc..) MAC packet statistics, FEC statistics etc.
2.  Link Analysis - Allows you to have transparency into the link bring up sequence (like Auto-negotiation, Link Training etc.) or any other event captured in the Signal Tap Logic Analyzer file. Configure & capture the Signal Tap Logic Analyzer file for given event and then use Link Analysis to import the captured event & study Stratix® 10 behavior during that event duration.
   

To access Ethernet Link Inspector for a specific Quartus® software version, please refer to the table below.

• For IP and Device support use model, refer to section ‘1.2 Supported IP Cores and Devices’ in the relevant Ethernet Link Inspector user guide.

Intellectual Property (IP) Core Release Notes

Agilex™ Devices

• E-Tile Hard IP for Ethernet Release Notes

Stratix® 10 Devices

• FPGA Triple Speed Ethernet IP Core Release Notes
• FPGA Low Latency Ethernet 10G MAC IP Core Release Notes
• Stratix® 10 10GBASE-KR PHY Release Notes
• Stratix® 10 H-Tile Hard IP for Ethernet IP Core Release Notes
• Stratix® 10 Low Latency 40-Gbps Ethernet IP Core Release Notes
• Stratix® 10 Low Latency 100-Gbps Ethernet IP Core Release Notes
• Stratix® 10 E-Tile Hard IP for Ethernet FPGA IP Release Notes

Arria® 10 Devices

• FPGA Triple Speed Ethernet IP Core Release Notes
• FPGA Low Latency Ethernet 10G MAC IP Core Release Notes
• 1G/10G and Backplane Ethernet 10GBASE-KR PHY Release Notes
• 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Release Notes
• 25G Ethernet IP Core Release Notes
• Low Latency 40Gbps Ethernet IP Core Release Notes
• Low Latency 100-Gbps Ethernet IP Core Release Notes

Cyclone® 10 Devices

• FPGA Triple Speed Ethernet IP Core Release Notes
• FPGA Low Latency Ethernet 10G MAC IP Core Release Notes

Fault Tree Analysis Guides

• Fault Tree Analysis Guide for Low Latency 10G MAC Data Corruption Issue

Knowledge Base Solutions

Agilex™ Devices

• Search the Knowledge Base (FPGA IP for Agilex™ FPGAs and SoC FPGAs)

Stratix® 10 Devices

• Search the Knowledge Base (FPGA IP for Triple Speed Ethernet)
• Search the Knowledge Base (FPGA IP for Low Latency Ethernet 10G MAC)
• Search the Knowledge Base (FPGA IP for 1G/2.5G/5G/10G Ethernet Multi-rate PHY)
• Search the Knowledge Base (FPGA IP for 25G Ethernet)
• Search the Knowledge Base (FPGA IP for Low Latency 40 Gbps Ethernet)
• Search the Knowledge Base (FPGA IP for Low Latency 100 Gbps Ethernet)

Arria® 10 Devices

• Search the Knowledge Base (FPGA IP for Triple-Speed Ethernet)
• Search the Knowledge Base (FPGA IP for Low Latency Ethernet 10G MAC)
• Search the Knowledge Base (FPGA IP for 1G/10G and Backplane Ethernet 10GBASE-KR PHY)
• Search the Knowledge Base (FPGA IP for 1G/2.5G/5G/10G Ethernet Multi-rate PHY)
• Search the Knowledge Base (FPGA IP for 25G Ethernet)
• Search the Knowledge Base (FPGA IP for Low Latency 40 Gbps Ethernet)
• Search the Knowledge Base (FPGA IP for Low Latency 100 Gbps Ethernet)

Cyclone® 10 Devices

• Search the Knowledge Base (FPGA IP for Triple Speed Ethernet)
• Search the Knowledge Base (FPGA IP for Low Latency Ethernet 10G MAC)

FPGA Technical Training

• Technical Training Catalog

6. Training Courses and Videos