1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
This design uses Intel's Low Latency Ethernet 10G Media Access Controller (MAC) and XAUI PHY IP cores with a dual XAUI small form factor pluggable plus (SFP+) high-speed mezzanine card (HSMC) board and FPGA mezzanine card (FMC) to high-speed mezzanine card (HSMC) adapter board on Arria® 10 FPGA development kit.
The design provides flexible test and demonstration platforms on which you can control, test, and monitor the Ethernet operations using system loopback at various points.
- Loopback points that include XGMII and serial physical medium attachment (PMA) interface in the Arria® 10 FPGA development board, and PMA interface in the Broadcom PHY BCM8727 chip on the Dual XAUI to SFP+ HSMC board.
- External optical loopback test at HSMC board SFP+ modules.
- Sequential random bursts tests. You can configure the number of packets, payload-data type, and payload size for each burst.
- Packet statistics for traffic generator, monitor, MAC transmitter (TX) and MAC receiver (RX).
- Packet classification for different frame sizes transmitted and received by the MAC.
- Throughput for the traffic received by the traffic monitor.
- System Console user interface. This TCL-based user interface allows you to dynamically configure and monitor any registers in the reference design.
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