1.1. Design Components
|Low Latency Ethernet 10G MAC IP Core||
This IP core handles the flow of data through the XAUI PHY IP core.
For this design, the MAC uses the memory-based statistics counters.
|XAUI PHY IP Core||
The XAUI PHY IP core sets to soft XAUI by default.
The traffic controller consists of:
The traffic controller connects to the Avalon-ST single-clock FIFO in the Ethernet subsystem through the Avalon Streaming (Avalon-ST) interface.
|Ethernet Packet Generator||
This module consists of Avalon Memory-Mapped (Avalon-MM) registers, Ethernet packet generation block, CRC generator, and shift register.
|Ethernet Packet Monitor||
This module verifies the payload of received packets and collects information from the statistics counters. This consists of Avalon-MM registers and CRC checkers.
|MDIO IP Core||
This IP core enables you to control the Broadcom PHY BCM8727 chip on the Dual XAUI to SFP+ HSMC board. You can access the external PHY registers through a pair of indirect registers to specify read or write operation, register address, port address, and device address.
|JTAG to Avalon Master Bridge||
This IP core provides a connection between the System Console and Qsys system through the physical interfaces. The System Console initiates Avalon-MM transactions by sending encoded streams of bytes through the bridge’s physical interfaces.
This module synchronizes and generates signals as per design requirements.
|Avalon-ST Single-Clock FIFO||
The Avalon-ST single-clock FIFO buffer receives and transmits data between the MAC and the client. The buffer is 64 bits wide and 512 bits deep. The buffer operates in store-and-forward mode by default. You can configure the buffer to enable the drop-on-error feature. When you enable the drop-on-error feature, the buffer drops the received packets when an error occurs.
This adapter converts the 32-bit Avalon-ST interface to 64 bits and vice verse.
Did you find the information on this page useful?