AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

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ID 683438
Date 2/01/2017
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design x
1.1. Design Components 1.2. Design Registers 1.3. Clock and Reset Signals 1.4. Hardware and Software Requirements 1.5. Board Setups 1.6. Testing the Design 1.7. Simulating the Design 1.8. Reference Design Debug Features 1.9. Revision History
1.6. Testing the Design x
1.6.1. Test Commands
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

1.6. Testing the Design

To make sure the design runs well, you must test the design on hardware.

The perform the hardware test, follow these steps:

  1. Download and restore the design.
  2. Launch the Quartus® Prime software and open the project file (top.qpf).
  3. Click Processing > Start Compilation to compile the design.
  4. Configure the FPGA using the generated configuration file (top.sof).
  5. When configuration completes, open the Clock Control application (arria10GX_10ax115sf45_fpga_v15.1.2\examples\board_test_system\ClockController.exe) and change the frequency for U14 CLK2 to 156.25 MHz.
  6. Reset the Ethernet system and HSMC board using the push button.
    You must reset the system whenever you begin a new test.
  7. On the Quartus® Prime software, click Tools > System Debugging Tools and launch the System Console.
  8. In the System Console command shell, change the directory to "system_console" directory.
  9. Run the following command to initialize the design:
    source demo.tcl
  10. Run the required tests using the provided test commands listed in Test Commands.
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