1.6. Testing the Design
The perform the hardware test, follow these steps:
- Download and restore the design.
- Launch the Quartus® Prime software and open the project file (top.qpf).
- Click to compile the design.
- Configure the FPGA using the generated configuration file (top.sof).
- When configuration completes, open the Clock Control application (arria10GX_10ax115sf45_fpga_v15.1.2\examples\board_test_system\ClockController.exe) and change the frequency for U14 CLK2 to 156.25 MHz.
- Reset the Ethernet system and HSMC board using the push button.
You must reset the system whenever you begin a new test.
- On the Quartus® Prime software, click and launch the System Console.
- In the System Console command shell, change the directory to "system_console" directory.
- Run the following command to initialize the design:
- Run the required tests using the provided test commands listed in Test Commands.
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