AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

ID 683438
Date 2/01/2017

1.6. Testing the Design

To make sure the design runs well, you must test the design on hardware.

The perform the hardware test, follow these steps:

  1. Download and restore the design.
  2. Launch the Quartus® Prime software and open the project file (top.qpf).
  3. Click Processing > Start Compilation to compile the design.
  4. Configure the FPGA using the generated configuration file (top.sof).
  5. When configuration completes, open the Clock Control application (arria10GX_10ax115sf45_fpga_v15.1.2\examples\board_test_system\ClockController.exe) and change the frequency for U14 CLK2 to 156.25 MHz.
  6. Reset the Ethernet system and HSMC board using the push button.
    You must reset the system whenever you begin a new test.
  7. On the Quartus® Prime software, click Tools > System Debugging Tools and launch the System Console.
  8. In the System Console command shell, change the directory to "system_console" directory.
  9. Run the following command to initialize the design:
    source demo.tcl
  10. Run the required tests using the provided test commands listed in Test Commands.