AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

ID 683438
Date 2/01/2017
Public

1.3. Clock and Reset Signals

The design uses different clock and reset signals for different components.
Table 5.  Clock and Reset Signals
Signal Direction Width Description
refclk1_p Input 1

100 MHz clock source used as IOPLL reference clock and Avalon-MM management clock

csr_clk Input 1 Configuration clock for the Avalon-MM interface, frequency is 100 MHz.
csr_rst_n Input 1 Reset Avalon-MM interface.
tx_312_5_clk Input 1 312.5 MHz clock for MAC TX data path.
rx_312_5_clk Input 1 312.5 MHz clock for MAC RX data path.
tx_156_25_clk Input 1 156.25 MHz clock for MAC TX data path.
rx_156_25_clk Input 1 156.25 MHz clock for MAC RX data path.
tx_rst_n Input 1 Active-low reset for MAC TX data path.
rx_rst_n Input 1 Active-low reset for MAC RX data path.
xgmii_156_25_clk Output 1 156.25 MHz output clock from fPLL.
mac_312_5_clk Output 1 312.5 MHz output clock from fPLL.
pll_ref_clk Input 1 Reference clock for ATX PLL, fPLL, and XAUI PHY.

Did you find the information on this page useful?

Characters remaining:

Feedback Message