AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

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ID 683438
Date 2/01/2017
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Document Table of Contents x
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design x
1.1. Design Components 1.2. Design Registers 1.3. Clock and Reset Signals 1.4. Hardware and Software Requirements 1.5. Board Setups 1.6. Testing the Design 1.7. Simulating the Design 1.8. Reference Design Debug Features 1.9. Revision History
1.6. Testing the Design x
1.6.1. Test Commands
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

1.2. Design Registers

You can use the registers to edit the design.
Table 2.  System Register MapThis table lists all the base addresses for components on the subsystems.
Component Base Address
Low latency 10G MAC 0x00000000
XAUI PHY 0x00008000
Generator 0x0000C000
Monitor 0x0000C400
Ethernet MDIO 0x0000B000
Avalon-ST single-clock FIFO (RX) 0x00009400
Avalon-ST single-clock FIFO (TX) 0x00009600
Table 3.  Generator Register MapThis table lists the generator registers for the traffic controller.
Byte Offset Name Width R/W Reset Value Description
0x00 NUMPKTS 32 RW 0x0 Number of packet registers. The total number of packets that the traffic generator generates and transmits to the 10GBASE-X Ethernet subsystem components.
0x04 RANDOMLENGTH 1 RW 0x0 Enables random length packets up to the maximum size defined by the PKTLENGTH register.
0x08 RANDOMPAYLOAD 1 RW 0x0 Enables random payload contents.
0x0C START 1 R/W 0x0 Write to this register to start the generation of the Ethernet traffic.
0x10 STOP 1 R/W 0x0 Stops the generation of the Ethernet traffic.
0x14 MACSA0 32 RW 0x0 Lower 32 bits of the Ethernet frame source address.
0x18 MACSA1 16 RW 0x0 Upper 16 bits of the Ethernet frame source address.
0x1C MACDA0 32 RW 0x0 Lower 32 bits of the Ethernet frame destination address.
0x2P MACDA1 16 RW 0x0 Upper 16 bits of the Ethernet frame destination address.
0x24 TXPKTCNT 32 RO 0x0 The number of packets that the traffic generator transmits. Read this register when the traffic generator is not active (e.g. after testing).
0x34 PKTLENGTH — R/W 0x0

The maximum length of any payload when random-sized packets are enabled.

Otherwise, this register defines the packet length generated by the traffic generator.

Table 4.  Monitor Register MapThis table lists the monitor registers for the traffic controller.
Byte Offset Name Width R/W Reset Value Description
0x00 RXPKTCNT_EXPT 32 RW 0xffffffff Number of packets that the traffic monitor expects.
0x04 RXPKTCNT_GOOD 32 RO 0x0 Number of good packets received by the traffic monitor.
0x08 RXPKTCNT_BAD 32 RO 0x0 Number of packets received with CRC error.
0x0C RXBYTECNT_LO32 32 RO 0x0 Lower 32 bits of the counter for bytes that the traffic monitor receives.
0x10 RXBYTECNT_HI32 32 RO 0x0 Upper 32 bits of the counter for bytes that the traffic monitor receives.
0x14 RXCYCLCNT_LO32 32 RO 0x0 Lower 32 bits of the counter for cycles that the traffic monitor uses to receive the expected number of packets.
0x18 RXCYCLCNT_HI32 32 RO 0x0 Upper 32 bits of the counter for cycles that the traffic monitor uses to receive the expected number of packets
0x1C RXCTRL_STATUS 10 RW/ RO 0x0
Monitor configuration and status register.
  • Bit[0]: Initializes all counters when 1’b1
  • Bit[1]: Reserved
  • Bit[2]: Read-only—sets when the traffic monitor has received all expected packets
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