AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

Download
ID 683438
Date 2/01/2017
Public
Document Table of Contents
Document Table of Contents
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
1.1. Design Components 1.2. Design Registers 1.3. Clock and Reset Signals 1.4. Hardware and Software Requirements 1.5. Board Setups 1.6. Testing the Design 1.7. Simulating the Design 1.8. Reference Design Debug Features 1.9. Revision History
1.6. Testing the Design
1.6.1. Test Commands
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

1.9. Revision History

Date Version Changes
February 2017 2017.02.01 Initial release.

Level Two Title

Did you find the information on this page useful?

Characters remaining:

Feedback Message