F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide
ID
781679
Date
10/07/2024
Public
1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver
3. F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide Archive
4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 24.3 |
| IP Version 22.4.0 |
The F-Tile Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 7 provides the capability of generating design examples for selected configurations, which allows you to:
- Compile the design to get an estimate of the IP area usage and timing.
- Simulate the design to verify the IP functionality through simulation.
- Test the design on the hardware using the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Production 1 4x F-Tile).
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Figure 1. Development Stages for the Design Example