F-Tile Triple-Speed Ethernet IP Design Example User Guide

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ID 781679
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver 3. F-Tile Triple-Speed Ethernet IP Design Example User Guide Archive 4. Document Revision History for the F-Tile Triple-Speed Ethernet IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the F-Tile Triple-Speed Ethernet IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure
1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver
3. F-Tile Triple-Speed Ethernet IP Design Example User Guide Archive
4. Document Revision History for the F-Tile Triple-Speed Ethernet IP Design Example User Guide

2.4. Simulation

The simulation test case performs the following steps:
  1. Instantiates Triple-Speed Ethernet IP and SYSPLL.
  2. Starts up the design example with an operating speed of 1G.
  3. Waits for RX clock and RX alignment to settle.
  4. Sends and receives 5 valid 32-bit data on 1G speed.
  5. Completes the simulation and displays End of Simulation.

When the testbench starts, it waits for rx_pcs_ready to go high. It then sends 5 packets to the TX Avalon® streaming interface and waits for those 5 packets to be received on the RX Avalon® streaming interface.


Section Content
Testbench

Level Two Title