Low Latency 40G Ethernet Example Design User Guide

ID 683413
Date 5/02/2016

1. Quick Start Guide

The Arria 10 variations of the LL 40 GbE IP core feature a simulatable testbench and a hardware example design that supports compilation and hardware testing, to help you understand usage. When you generate the example design, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware. You can download the compiled hardware design to the Arria 10 GX Transceiver Signal Integrity Development Kit. The testbench and demonstration example design are available for a wide range of parameters. However, they do not cover all possible parameterizations of the LL 40 GbE IP Core.

In addition, for most IP core variations, Altera provides a compilation-only example project that you can use to quickly estimate IP core area and timing.

Figure 1. Development Steps for the Example Design