Low Latency 40G Ethernet Example Design User Guide

Download PDF
ID 683413
Date 5/02/2016
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Example Design Description A. Document Revision History
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Example Design in Hardware
2. Example Design Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Design Variations 2.5. Interface Signals 2.6. Example Design Registers
2.4. Design Variations x
2.4.1. Standard IP Core Variation 2.4.2. 40GBASE-KR4 IP Core Variation
1. Quick Start Guide
2. Example Design Description
A. Document Revision History

1.5. Compiling and Testing the Example Design in Hardware

To compile and run a demonstration test on the hardware design example, follow these steps:

  1. Ensure hardware design example generation is complete.
  2. In the Quartus® Prime software, open the Quartus® Prime project <example_design_install_dir>/hardware_test_design/eth_ex_40 g_a10.qpf, as appropriate.
  3. On the Processing menu, click Start Compilation.
  4. After successful compilation, a .sof file will be generated in your specified directory. Follow these steps to program the hardware design example on the Arria 10 device:
    1. On the Tools menu, click Programmer.
    2. In the Programmer, click Hardware Setup.
    3. Select a programming device.
    4. Select and add the Arria 10 GX Transceiver Signal Integrity Development Kit to which your Quartus® Prime session can connect.
    5. Ensure that Mode is set to JTAG.
    6. Select the Arria 10 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    7. In the row with your .sof, check the box for the .sof.
    8. Check the box in the Program/Configure column.
    9. Click Start.
    10. After the hardware example design is configured on the Arria 10 device, in the Quartus® Prime software, on the Tools menu, click System Debugging Tools > System Console.
  5. In the Tcl Console pane, type cd hwtest to change directory to <example_design_install_dir>/hardware_test_design/hwtest.
  6. Type source main.tcl.
  7. Type run_test.

The successful test run displays output confirming the following behavior:

  1. Turning off packet generation
  2. Enabling loopback
  3. Waiting for RX clock to settle
  4. Printing PHY status
  5. Clearing MAC statistics counters
  6. Sending packets
  7. Reading MAC statistics counters
  8. Printing MAC statistics counters, which show 0 in all error counters

The following sample output illustrates a successful test run:


--- Turning off packet generation ---- 
--------------------------------------

--------- Enabling loopback ----------
--------------------------------------

--- Wait for RX clock to settle... ---
--------------------------------------

-------- Printing PHY status ---------
--------------------------------------

 RX PHY Register Access: Checking Clock Frequencies (KHz)

          REFCLK                :644530 (KHZ)
          TXCLK                 :390624   (KHZ)
          RXCLK                 :390625   (KHZ)
          RX RECOV CLK          :322265   (KHZ)
          TX-IO CLOCK           :322265   (KHZ)
 RX PHY Status Polling

 Tx PLL Lock Status             0x000003ff

 Rx Frequency Lock Status       0x000003ff

 Mac Clock in OK Condition?     0x00000007

 Rx Frame Error                 0x00000000

 Rx PHY Fullly Aligned?         0x00000001

---- Clearing MAC stats counters -----
--------------------------------------

--------- Sending packets... ---------
--------------------------------------

----- Reading MAC stats counters -----
--------------------------------------


 ======================================================================
                        STATISTICS FOR BASE 0x0900 (Rx)
 ======================================================================
Fragmented Frames                : 0
Jabbered Frames                  : 0
Any Size with FCS Err Frame      : 0
Right Size with FCS Err Fra      : 0
Multicast data Err Frames        : 0
Broadcast data Err Frames        : 0
Unicast data Err  Frames         : 0
Multicast control  Err Frame     : 0
Broadcast control Err  Frame     : 0
Unicast control Err Frames       : 0
Pause control Err Frames         : 0
64 Byte Frames                   : 0
65 - 127 Byte Frames             : 6894742
128 - 255 Byte Frames            : 9147409
256 - 511 Byte Frames            : 8089346
512 - 1023 Byte Frames           : 3411180
1024 - 1518 Byte Frames          : 347630
1519 - MAX Byte Frames           : 40042
> MAX Byte Frames                : 0
Rx Frame Starts                  : 27930349
Multicast data OK  Frame         : 0
Broadcast data OK  Frame         : 0
Unicast data OK  Frames          : 27929934
Multicast Control Frames         : 0
Broadcast Control Frames         : 0
Unicast Control Frames           : 415
Pause Control Frames             : 0
 ======================================================================
                        STATISTICS FOR BASE 0x0800 (Tx)
 ======================================================================
Fragmented Frames                : 0
Jabbered Frames                  : 0
Any Size with FCS Err Frame      : 0
Right Size with FCS Err Fra      : 0
Multicast data Err Frames        : 0
Broadcast data Err Frames        : 0
Unicast data Err Frames          : 0
Multicast control  Err Frame     : 0
Broadcast control Err  Frame     : 0
Unicast control Err Frames       : 0
Pause control Err Frames         : 0
64 Byte Frames                   : 0
65 - 127 Byte Frames             : 6894742
128 - 255 Byte Frames            : 9147409
256 - 511 Byte Frames            : 8089346
512 - 1023 Byte Frames           : 3411180
1024 - 1518 Byte Frames          : 347630
1519 - MAX Byte Frames           : 40042
> MAX Byte Frames                : 0
Tx Frame Starts                  : 27930349
Multicast data OK  Frame         : 0
Broadcast data OK  Frame         : 0
Unicast data OK  Frames          : 27929934
Multicast Control Frames         : 0
Broadcast Control Frames         : 0
Unicast Control Frames           : 415
Pause Control Frames             : 0
---------------- Done ----------------
Related Information
Level Two Title