Low Latency 40G Ethernet Example Design User Guide

ID 683413
Date 5/02/2016

1.4. Simulating the Design

Figure 6. Procedure
Table 1.  Low Latency 40 GbE IP Core Testbench File DescriptionsLists the key files that implement the example testbenches.

File Names


Testbench and Simulation Files

basic_avl_tb_top.v Top-level testbench file for non-40GBASE-KR4 variations. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.
alt_e40_avalon_kr4_tb.sv Top-level testbench file for 40GBASE-KR4 variations.
alt_e40_avalon_tb_packet_gen.v, alt_e40_avalon_tb_packet_gen_sanity_check.v, alt_e40_stat_cntr_1port.v Packet generator and checkers for 40GBASE-KR4 variations.

Testbench Scripts


The ModelSim script to run the testbench.


The Synopsys VCS script to run the testbench.


The Cadence NCSim script to run the testbench.

Follow these steps to simulate the testbench:

  1. Change to the testbench simulation directory <example_design_install_dir>/example_testbench.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table "Steps to Simulate the Testbench".
  3. Analyze the results. The successful testbench sends ten packets, receives ten packets, and displays "Testbench complete."
    Table 2.  Steps to Simulate the Testbench
    Simulator Instructions
    Modelsim In the command line, type vsim -c -do run_vsim.do
    Note: The ModelSim-AE simulator does not have the capacity to simulate this IP core. You must use another supported ModelSim simulator.
    NCSim In the command line, type sh run_ncsim.sh
    VCS In the command line, type sh run_vcs.sh