Low Latency 40G Ethernet Example Design User Guide

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ID 683413
Date 5/02/2016
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Example Design Description A. Document Revision History
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Example Design in Hardware
2. Example Design Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Design Variations 2.5. Interface Signals 2.6. Example Design Registers
2.4. Design Variations x
2.4.1. Standard IP Core Variation 2.4.2. 40GBASE-KR4 IP Core Variation
1. Quick Start Guide
2. Example Design Description
A. Document Revision History

2.3. Functional Description

Figure 7. High Level Block Diagram for the LL 40 GbE Hardware Design Example
The Arria 10 Low Latency 40 GbE hardware design example includes the following components:
  • Low Latency 40 GbE IP core with Avalon-ST user interfaces. The IP core does not support a hardware example design for variations with custom streaming user interfaces.
  • Client logic that coordinates the programming of the IP core, and packet generation and checking.
  • JTAG controller that communicates with the Altera System Console. You communicate with the client logic through the System Console.
Table 3.  Low Latency GbE IP Core Hardware Design Example File Descriptions

File Names

Description

eth_ex_40 g_a10.qpf Quartus Prime project file
eth_ex_40 g_a10.qsf Quartus project settings file
eth_ex_40 g_a10.v Top-level Verilog HDL design example file
common/ Hardware design example support files

Scripts
hwtest/

System Console testing scripts
hwtest/main.tcl

Main file for accessing System Console
Related Information
Level Two Title