2.3. Functional Description
- Low Latency 40 GbE IP core with Avalon-ST user interfaces. The IP core does not support a hardware example design for variations with custom streaming user interfaces.
- Client logic that coordinates the programming of the IP core, and packet generation and checking.
- JTAG controller that communicates with the Altera System Console. You communicate with the client logic through the System Console.
|eth_ex_40 g_a10.qpf||Quartus Prime project file|
|eth_ex_40 g_a10.qsf||Quartus project settings file|
|eth_ex_40 g_a10.v||Top-level Verilog HDL design example file|
|common/||Hardware design example support files|
System Console testing scripts
Main file for accessing System Console
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