Low Latency 40G Ethernet Example Design User Guide

ID 683413
Date 5/02/2016

2.3. Functional Description

Figure 7. High Level Block Diagram for the LL 40 GbE Hardware Design Example
The Arria 10 Low Latency 40 GbE hardware design example includes the following components:
  • Low Latency 40 GbE IP core with Avalon-ST user interfaces. The IP core does not support a hardware example design for variations with custom streaming user interfaces.
  • Client logic that coordinates the programming of the IP core, and packet generation and checking.
  • JTAG controller that communicates with the Altera System Console. You communicate with the client logic through the System Console.
Table 3.  Low Latency GbE IP Core Hardware Design Example File Descriptions

File Names


eth_ex_40 g_a10.qpf Quartus Prime project file
eth_ex_40 g_a10.qsf Quartus project settings file
eth_ex_40 g_a10.v Top-level Verilog HDL design example file
common/ Hardware design example support files



System Console testing scripts


Main file for accessing System Console

Did you find the information on this page useful?

Characters remaining:

Feedback Message