Low Latency 40G Ethernet Example Design User Guide

Download PDF
ID 683413
Date 5/02/2016
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Example Design Description A. Document Revision History
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Example Design in Hardware
2. Example Design Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Design Variations 2.5. Interface Signals 2.6. Example Design Registers
2.4. Design Variations x
2.4.1. Standard IP Core Variation 2.4.2. 40GBASE-KR4 IP Core Variation
1. Quick Start Guide
2. Example Design Description
A. Document Revision History
Give Feedback

2.5. Interface Signals

Table 4.  Example Design Interface Signals
Signal Direction Interface
clk_ref Input Clocks
reset_async Input Reset
tx_serial[3:0] / tx_serial[9:0] Output Transceiver PHY serial data interface
Related Information
Level Two Title