Low Latency 40G Ethernet Example Design User Guide

ID 683413
Date 5/02/2016

2.4.1. Standard IP Core Variation

The example design for standard 40 GbE IP core variations that target an Arria 10 device configure a single ATX PLL and connect it to the xN clock network, which distributes the output tx_serial_clk signal to all four or ten individual transceiver channels. If this arrangement is not available for your design, you can use multiple external ATX and CMU PLLs to generate and distribute the tx_serial_clk signals for the individual channels. It also includes client logic to exercise the IP core. The client logic includes logic to ensure each packet is sent to the Avalon-ST interface without any intermediate idle cycles, in other words, that the data sent to this interface complies with the IP core requirements.
Figure 8. IP Core Variation Testbench
The simulation testbench instantiates the IP core and necessary PLLs. It interfaces directly with the Avalon-ST port to provide basic packet sending and receiving. The TX and RX lanes will be connected together to provide loopback testing capabilities.