AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices

Download PDF
ID 683347
Date 10/28/2020
Public
Document Table of Contents
Document Table of Contents x
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices x
1.1. Low Latency Ethernet 10G MAC and Intel® Arria® 10 Transceiver Native PHY Intel® FPGA IPs 1.2. Low Latency Ethernet 10G MAC and XAUI PHY Intel® FPGA IPs 1.3. Low Latency Ethernet 10G MAC and 1G/10GbE and 10GBASE-KR PHY Intel® Arria® 10 FPGA IPs 1.4. Low Latency Ethernet 10G MAC and 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel® FPGA IPs 1.5. Document Revision History for AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices

1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices

The implementing guidelines show you how to use Intel's Low Latency 10G Media Access Controller (MAC) and PHY IPs.
Figure 1.  Intel® Arria® 10 Low Latency Ethernet 10G MAC System
Table 1.   Intel® Arria® 10 Low Latency Ethernet 10G MAC DesignsThis table lists all the Intel® Arria® 10 designs for Low Latency Ethernet 10G MAC Intel® FPGA IP.
Design Example MAC Variant PHY Development Kit
10GBase-R Ethernet 10G Native PHY Intel® Arria® 10 GX Transceiver SI
10GBase-R Register Mode Ethernet 10G Native PHY Intel® Arria® 10 GX Transceiver SI
XAUI Ethernet 10G XAUI PHY Intel® Arria® 10 GX FPGA
1G/10G Ethernet 1G/10G 1G/10GbE and 10GBASE-KR PHY Intel® Arria® 10 GX Transceiver SI
1G/10G Ethernet with 1588 1G/10G 1G/10GbE and 10GBASE-KR PHY Intel® Arria® 10 GX Transceiver SI
10M/100M/1G/10G Ethernet 10M/100M/1G/10G 1G/10GbE and 10GBASE-KR PHY Intel® Arria® 10 GX Transceiver SI
10M/100M/1G/10G Ethernet with 1588 10M/100M/1G/10G 1G/10GbE and 10GBASE-KR PHY Intel® Arria® 10 GX Transceiver SI
1G/2.5G Ethernet 1G/2.5G

1G/2.5G/5G/10G

Multi-rate Ethernet PHY 		Intel® Arria® 10 GX Transceiver SI
1G/2.5G Ethernet with 1588 1G/2.5G

1G/2.5G/5G/10G

Multi-rate Ethernet PHY 		Intel® Arria® 10 GX Transceiver SI
1G/2.5G/10G Ethernet 1G/2.5G/10G

1G/2.5G/5G/10G

Multi-rate Ethernet PHY 		Intel® Arria® 10 GX Transceiver SI
10G USXGMII Ethernet 1G/2.5G/5G/10G (USXGMII)

1G/2.5G/5G/10G

Multi-rate Ethernet PHY 		Intel® Arria® 10 GX Transceiver SI
Note: You can access all the listed designs through the Low Latency Ethernet 10G MAC Intel® FPGA IP parameter editor in the Intel® Quartus® Prime software, except for the XAUI Ethernet reference design. You can get the XAUI Ethernet reference design from the Design Store.

Intel offers separate MAC and PHY IPs for the 10M to 1G Multi-rate Ethernet subsystems to ensure flexible implementation. You can instantiate the Low Latency Ethernet 10G MAC Intel® FPGA IP with 1G/2.5G/5G/10G Multi-rate Ethernet PHY, Intel® Arria® 10 1G/10GbE and 10GBASE-KR PHY, or XAUI PHY and Intel® Arria® 10 Transceiver Native PHY to cater different design requirements.

Related Information
Level Two Title