AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices

Download PDF
ID 683347
Date 10/28/2020
Public
Document Table of Contents
Document Table of Contents x
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices x
1.1. Low Latency Ethernet 10G MAC and Intel® Arria® 10 Transceiver Native PHY Intel® FPGA IPs 1.2. Low Latency Ethernet 10G MAC and XAUI PHY Intel® FPGA IPs 1.3. Low Latency Ethernet 10G MAC and 1G/10GbE and 10GBASE-KR PHY Intel® Arria® 10 FPGA IPs 1.4. Low Latency Ethernet 10G MAC and 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel® FPGA IPs 1.5. Document Revision History for AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices

1.5. Document Revision History for AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices

Document Version Changes
2020.10.28
  • Rebranded as Intel.
  • Renamed the document as AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices.
Date Version Changes
February 2017 2017.02.01 Initial release.

Level Two Title