AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design

Download
ID 683167
Date 5/19/2021
Public
Document Table of Contents
Document Table of Contents
1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices
1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices
1.1. Features 1.2. Hardware and Software Requirements 1.3. Functional Description 1.4. Hardware Testing 1.5. TCL Script 1.6. Interface Signals 1.7. Configuration Registers and Status Registers 1.8. Regenerating Triple-Speed Ethernet Intel® FPGA IP 1.9. Document Revision History for AN 830: Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices
1.3. Functional Description
1.3.1. Design Components 1.3.2. Clocking Scheme 1.3.3. Reset Scheme
1.4. Hardware Testing
1.4.1. Test Case—Internal MAC Loopback 1.4.2. Test Case— Avalon® Streaming Reverse Loopback
1.5. TCL Script
1.5.1. Configuration Script 1.5.2. Ethernet Packet Generator Script
1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices

1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices

The Intel® FPGA Triple-Speed Ethernet and on-board PHY chip reference design demonstrates Ethernet operation between the Triple-Speed Ethernet Intel® FPGA IP core and on-board Marvell 88E1111 PHY chip in Intel® Stratix® 10 GX FPGA Development Board. In this reference design, the Triple-Speed Ethernet Intel® FPGA IP is connected to the on-board PHY chip through Serial Gigabit Media Independent Interface (SGMII).

Level Two Title

Did you find the information on this page useful?

Characters remaining:

Feedback Message