AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design

ID 683167
Date 5/19/2021
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1.1. Features

  • Single-channel Triple-Speed Ethernet Intel® FPGA IP operating at data rate of 10/100/1000 Mbps.
  • Implementation of the SGMII auto-negotiation feature in order to communicate with on-board PHY chip.
  • Sequential random burst test is supported in the hardware test and users are allowed to configure the number of packets, payload-data pattern, packet length, source MAC address, and destination MAC address of each burst.
  • Support for Ethernet packet transmission and reception through internal MAC loopback path or Avalon® streaming reverse loopback path.
  • Support for packet monitoring on both TX and RX data paths.
  • Support for packet statistics report on both MAC transmitter (TX) and MAC receiver (RX).
  • Support for System Console user interface. Users can make use of this TCL-based interface to dynamically configure and monitor any registers in this reference design.