AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design

ID 683167
Date 5/19/2021
Public

1.6. Interface Signals

Table 3.  Clock and Reset Signals
Signal Direction Width Description
clk_clk Input 1 This is the reference design clock, which derived from the IOPLL Intel® FPGA IP.
reset_reset Input 1 A single reset signal that used to reset all logic in the reference design. This reset signal is connected to a push button (USER_PB0).
triple_speed_ethernet_0_pcs_ ref_clk_clock_connection_clk Input 1 The 125 MHz reference clock for the 1.25 Gbps serial LVDS I/O interface. This clock is sourced from a dedicated reference clock source, which is in the same IO bank as triple_speed_ethernet_0_ serial_connection_txp_0 and triple_speed_ethernet_0_ serial_connection_rxp_0 pins.
Table 4.  1.25 Gbps Serial Interface Signals
Signal Direction Width Description
triple_speed_ethernet_0_ serial_connection_txp_0 Output 1 SGMII serial differential transmit interface. Connect this interface to the on-board PHY chip.
triple_speed_ethernet_0_ serial_connection_rxp_0 Input 1 SGMII serial differential receive interface. Connect this interface to the on-board PHY chip.

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