AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design

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ID 683167
Date 5/19/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices
1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Functional Description 1.4. Hardware Testing 1.5. TCL Script 1.6. Interface Signals 1.7. Configuration Registers and Status Registers 1.8. Regenerating Triple-Speed Ethernet Intel® FPGA IP 1.9. Document Revision History for AN 830: Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices
1.3. Functional Description x
1.3.1. Design Components 1.3.2. Clocking Scheme 1.3.3. Reset Scheme
1.4. Hardware Testing x
1.4.1. Test Case—Internal MAC Loopback 1.4.2. Test Case— Avalon® Streaming Reverse Loopback
1.5. TCL Script x
1.5.1. Configuration Script 1.5.2. Ethernet Packet Generator Script
1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices

1.8. Regenerating Triple-Speed Ethernet Intel® FPGA IP

The on-chip termination of the LVDS SERDES Intel® FPGA IP reference clock within the Triple-Speed Ethernet Intel® FPGA IP is turned on by default. The reference clock is pinned out to REF_CLK port in this reference design. Because an external termination resistor is present on the Intel® Stratix® 10 GX FPGA Development Kit at the REF_CLK port, the generated QIP file of the Triple-Speed Ethernet Intel® FPGA IP is modified to turn off the on-chip termination. When upgrading the reference design to a newer Intel® Quartus® Prime software version or modification is made to the Triple-Speed Ethernet Intel® FPGA IP, the QIP file is regenerated as part of the IP regeneration process. To turn off the on-chip termination, follow these steps to modify the QIP file after the IP regeneration:
  1. Locate the QIP file of the Triple-Speed Ethernet Intel® FPGA IP at <project_directory>/platform/ip/qsys_top/qsys_top_eth_tse_0/qsys_top_eth_tse_0.qip
  2. Search the INPUT_TERMINATION keyword for the LVDS SERDES Intel® FPGA IP reference clock: 
    set_instance_assignment -entity "qsys_top_eth_tse_0_altera_lvds_core14_191_ofc4bti" -library "altera_lvds_core14_191" -name INPUT_TERMINATION DIFFERENTIAL -to inclock
  3. Comment out or remove this assignment.
  4. Compile the reference design.
    Failure to follow these steps will result in a critical warning: 
    Critical Warning(16643): Found INPUT_TERMINATION assignments found for "REF_CLK" pin with multiple values. Using value: "OFF"
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