AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design

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ID 683167
Date 5/19/2021
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices
1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Functional Description 1.4. Hardware Testing 1.5. TCL Script 1.6. Interface Signals 1.7. Configuration Registers and Status Registers 1.8. Regenerating Triple-Speed Ethernet Intel® FPGA IP 1.9. Document Revision History for AN 830: Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices
1.3. Functional Description x
1.3.1. Design Components 1.3.2. Clocking Scheme 1.3.3. Reset Scheme
1.4. Hardware Testing x
1.4.1. Test Case—Internal MAC Loopback 1.4.2. Test Case— Avalon® Streaming Reverse Loopback
1.5. TCL Script x
1.5.1. Configuration Script 1.5.2. Ethernet Packet Generator Script
1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices

1.7. Configuration Registers and Status Registers

Table 5.   System Register Map
Base Address Block
0x00000000 Triple-Speed Ethernet Intel® FPGA IP
0x00000400 Avalon® Streaming Multiplexer
0x00000800 Ethernet Packet Monitor
0x00000C00 Ethernet Packet Generator
Table 6.  Ethernet Packet Generator Configuration Registers Map
Byte Offset Name Width R/W HW Reset Value Description
0x00 number_packet 32 RW 0x00 Used to specify the number of packets to be generated.
0x04 config_register 32 RW 0x00
  • Bit 0
    • 0: Fixed packet length
    • 1: Random packet length
  • Bits [14:1]—Specifies the fixed packet length and the valid values are between 24 to 9600 bytes. It is applicable only when you set bit 0 to 0.
  • Bit 15—Specifies the data pattern for random packet length. Set this bit to 0 for incremental data pattern. For random data pattern, set this bit to 1.
  • Bits [31:16]—Reserved.
0x08 rand_seed0 32 RW 0x00
  • The lower 32 bits of the random seed.
  • Occupies bits 31:0 of the PBRS generator when you set the data pattern to random (bit 15 of the configuration register).
0x0c rand_seed1 32 RW 0x00
  • The upper 32 bits of the random seed.
  • Occupies bits 63:32 of the PBRS generator when you set the data pattern to random (bit 15 of the configuration register).
0x10 source_addr0 32 RW 0x00
  • Used to specify 6-bytes source/destination MAC address.
  • source_addr0/destination_addr0 = last four bytes of the address
  • Bits [15:0] of source_addr1/destination_addr1 = first two bytes of the address
  • Bits [31:16] of source_addr1/destination_addr1 = unused
  • For example, if the source MAC address is 00-1C-23-17-4A-CB, you get the following assignments:
    • source_addr0 = 0x17231C00
    • source_addr1 = 0x0000CB4A
0x14 source_addr1 32 RW 0x00
0x18 destination_addr0 32 RW 0x00
0x1C destination_addr1 32 RW 0x00
0x20 operation 32 RW/RO 0x00
  • Bit 0—Set this bit to 1 to trigger packet generation. This bit clears after the packet generation is started.
  • Bit 1—Set this bit to 1 to stop the packets generation. The generator will complete its current packet transmission 1st before terminates the packet generation.
  • Bit 2—A value of 1 indicates that the packet generator completes generating the total number of packets specified in the number_packet register. This bit clears each time packet generation triggers.
  • Bit [31:3]—Reserved.
0x24 packet_tx_count 32 RO 0x00 This register will keep track the number of packets that the generator transmitted successfully. This register will clear if the packet generation is triggered.
Table 7.  Ethernet Packet Monitor Configuration Registers Map
Byte Offset Name Width R/W HW Reset Value Description
0x00 number_packet 32 RO 0x00 Total number of packets that the monitor expects to receive.
0x04 packet_rx_ok 32 RO 0x00 Total number of received good packets.
0x08 packet_rx_error 32 RO 0x00 Total number of received packets with errors.
0x0C byte_rx_count[31:0] 32 RO 0x00
  • 64-bit counter that keeps track of the total number of bytes received.
  • byte_rx_count[31:0] represents the lower 32 bits.
  • byte_rx_count[63:32] represents the upper 32 bits.
  • Read byte_rx_count[31:0] followed by byte_rx_count[63:32] in the subsequent cycle to get an accurate count.
0x10 byte_rx_count[63:32] 32 RO 0x00
0x14 cycle_rx_count[31:0] 32 RO 0x00
  • 64-bit counter that keeps track of the total number of cycles the monitor takes to receive all packets.
  • cycle_rx_count[31:0] represents the lower 32 bits.
  • cycle_rx_count[63:32] represents the upper 32 bits.
  • Read cycle_rx_count[31:0] followed by cycle_rx_count[63:32] in the subsequent cycle to get an accurate count.
0x18 cycle_rx_count[63:32] 32 RO 0x00
0x1C rx_control_status 32 RW/RO 0x00
  • Bit 0—Set this bit to 1 to trigger packets reception. This bit clears after packet reception is started.
  • Bit 1—Set this bit to 1 to stop packet reception. This bit clears when packet reception starts.
  • Bit 2—A value of 1 indicates that the packet monitor has received the total number of packets specified in the number_packet register.
  • Bit 3—A value of 1 indicates that the current packet received by monitor has CRC error.
  • Bits [9:4]—Receive error status. The behavior of rx_err signal in Triple-Speed Ethernet Intel® FPGA IP is mapped to this register.
  • Bits [31:10]—Reserved.
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